利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

28 条记录 (耗时 0.031 秒)

    Multiplex execution-path system
    3.
    发明授权
    Multiplex execution-path system 失效
    多路复用执行路径系统

    公开(公告)号：US07340595B2

    公开(公告)日：2008-03-04

    申请号：US11031605

    申请日：2005-01-07

    申请人： Stephen L. Blinick ,  Charles S. Cardinell ,  Ricardo S. Padilla

    发明人： Stephen L. Blinick ,  Charles S. Cardinell ,  Ricardo S. Padilla

    IPC分类号： G06F9/445 ,  G06F15/177

    CPC分类号： G06F11/1417 ,  G06F11/1666 ,  G06F11/2284

    摘要： A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the predetermined offset address being added to the current instruction address. If corrupted data is encountered in the secondary executables, the offset bit is reset. An optional redundant flash image may also be used. A failure at the same relative address in the primary and secondary executables of the main flash image will cause the exception handler to transfer control to the redundant flash image. A subsequent failure at the same relative address in the primary and secondary executables of the redundant flash image will cause the redundant exception handler to transfer control back to the main flash image.

    摘要翻译： 多个执行路径闪存系统包括主闪存映像，主要和辅助POST和引导可执行文件。 次级可执行文件与主要可执行文件偏移预定的偏移地址。 如果在引导期间遇到损坏的数据，则异常处理程序设置偏移位，导致预定的偏移地址被添加到当前指令地址。 如果在二级可执行文件中遇到损坏的数据，则偏移位被复位。 也可以使用可选的冗余闪光图像。 在主闪存映像的主要和次要可执行文件中的相同相对地址的故障将导致异常处理程序将控制传输到冗余闪存映像。 冗余闪存映像的主要和次要可执行文件中的相同相对地址的后续故障将导致冗余异常处理程序将控制权传输回主Flash映像。

    SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING
    7.
    发明申请
    SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING 有权
    用于写入累积和分析的二次高速缓存

    公开(公告)号：US20120191904A1

    公开(公告)日：2012-07-26

    申请号：US13430613

    申请日：2012-03-26

    申请人： Stephen L. Blinick ,  Lokesh M. Gupta ,  Yu-Cheng Hsu ,  Cheng-Chung Song

    发明人： Stephen L. Blinick ,  Lokesh M. Gupta ,  Yu-Cheng Hsu ,  Cheng-Chung Song

    IPC分类号： G06F12/02 ,  G06F12/08

    CPC分类号： G06F12/0804 ,  G06F11/1008 ,  G06F11/1076 ,  G06F12/0866

    摘要： A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein.

    摘要翻译： 本文公开了一种高效地使用大型二级高速缓存的方法。 在某些实施例中，这种方法可以包括在二次高速缓存中累积多个数据轨道。 这些数据轨道可以包括经修改的数据和/或未修改的数据。 该方法可以确定多个数据轨道的一个子集是否构成一个完整的步幅。 在子集构成一个完整的步骤的情况下，该方法可能会从二级缓存中退出该子集。 通过降级整个步骤，该方法减少了从二级缓存中恢复数据所需的磁盘操作数。 本文还公开了相应的计算机程序产品和装置。

    MULTI-CHARACTER ADAPTER CARD
    8.
    发明申请
    MULTI-CHARACTER ADAPTER CARD 失效
    多字符适配卡

    公开(公告)号：US20080301345A1

    公开(公告)日：2008-12-04

    申请号：US11754821

    申请日：2007-05-29

    申请人： Stephen L. Blinick ,  Carol Spanel ,  Andrew Dale Walls

    发明人： Stephen L. Blinick ,  Carol Spanel ,  Andrew Dale Walls

    IPC分类号： G06F13/00

    CPC分类号： G06F13/385

    摘要： One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.

    摘要翻译： 根据本发明的适配器卡的一个实施例包括可连接到计算机系统的主板的电路板。 逻辑芯片连接到电路板以向适配器卡提供功能。 一个或多个可编程设备连接到电路板，并在初始化时存储由逻辑芯片读取的数据。 该数据可以包括用于对逻辑芯片编程以具有第一字符和第二字符数据的第一字符数据，以将逻辑芯片编程为具有第二字符。 提供切换机制以响应于外部输入在第一和第二字符数据之间切换，从而使逻辑芯片读取第一和第二字符数据之一。

    Non-disruptive code update of a single processor in a multi-processor computing system
    9.
    发明授权
    Non-disruptive code update of a single processor in a multi-processor computing system 有权
    多处理器计算系统中单个处理器的无中断代码更新

    公开(公告)号：US08898653B2

    公开(公告)日：2014-11-25

    申请号：US11769083

    申请日：2007-06-27

    申请人： Stephen L. Blinick ,  Chiahong Chen

    发明人： Stephen L. Blinick ,  Chiahong Chen

    IPC分类号： G06F9/44 ,  G06F9/445

    CPC分类号： G06F9/44505 ,  G06F8/65 ,  G06F9/4401

    摘要： Updating code of a single processor in a multi-processor system includes halting transactions processed by a first processor in the system and processing of transactions by a second processor in the system are maintained. The first processor then receives new code and an operating system running on the first processor is terminated whereby all processes and threads being executed by the first processor are terminated. Execution of a self-reset of the first processor is commenced and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor.

    摘要翻译： 在多处理器系统中更新单个处理器的代码包括停止由系统中的第一处理器处理的事务，并且维护由系统中的第二处理器处理事务的处理。 然后，第一处理器接收新的代码，并且终止在第一处理器上运行的操作系统，由此终止由第一处理器执行的所有进程和线程。 开始执行第一处理器的自复位，并且禁用与第一处理器相关联的中断。 只有与第一处理器完全相关联的系统资源被重置，并且与第一处理器相关联的存储器事务被禁用。 将新代码的图像复制到与第一处理器相关联的存储器中，与第一处理器相关联的寄存器被复位，并且新代码由第一处理器引导。