公开(公告)号：US07523852B2

公开(公告)日：2009-04-28

申请号：US11005557

申请日：2004-12-05

申请人： Stephen L. Buchwalter ,  Claudius Feger ,  Peter A. Gruber ,  Sung K. Kang ,  Paul A. Lauro ,  Da-Yuan Shih

发明人： Stephen L. Buchwalter ,  Claudius Feger ,  Peter A. Gruber ,  Sung K. Kang ,  Paul A. Lauro ,  Da-Yuan Shih

IPC分类号： B23K35/12

CPC分类号： H05K3/3436 ,  B23K35/26 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/1357 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K3/3426 ,  H05K3/3468 ,  H05K2201/10287 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/0415 ,  H05K2203/128 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Improved interconnects are produced by injection molded solder which fills mold arrays with molten solder so that columns that have much greater height to width aspect ratios greater than one are formed, rather than conventional flip chip bumps. The columns may have filler particles or reinforcing conductors therein. In the interconnect structures produced, the cost and time of a subsequent underfill step is reduced or avoided. The problem of incompatibility with optical interconnects between chips because underfills require high loading of silica fillers which scatter light, is solved, thus allowing flip chips to incorporate optical interconnects.

摘要翻译： 改进的互连通过注射成型的焊料生产，该焊料用熔融焊料填充模具阵列，使得形成具有大于1的高宽比宽高比的柱而不是传统的倒装芯片凸块。 该列可以在其中具有填料颗粒或增强导体。 在所生产的互连结构中，减少或避免了后续底部填充步骤的成本和时间。 与芯片之间的光学互连不兼容的问题，因为底部填充物需要高散射光的二氧化硅填料的高负载，因此可以使倒装芯片结合光学互连。

公开(公告)号：US08314500B2

公开(公告)日：2012-11-20

申请号：US11616919

申请日：2006-12-28

申请人： Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valérie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K Srivastava ,  Michael J. Sullivan

发明人： Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valérie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K Srivastava ,  Michael J. Sullivan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2224/13099

摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

摘要翻译： 一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层 无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。 一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

公开(公告)号：US20100062597A1

公开(公告)日：2010-03-11

申请号：US12587301

申请日：2009-10-05

申请人： Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valérie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K. Srivastava ,  Michael J. Sullivan

发明人： Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valérie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K. Srivastava ,  Michael J. Sullivan

IPC分类号： H01L21/60

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2224/13099

摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

摘要翻译： 一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层 无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。 一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

公开(公告)号：US07452568B2

公开(公告)日：2008-11-18

申请号：US11049846

申请日：2005-02-04

申请人： Gareth Hougham ,  Leena Paivikki Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelorme ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

发明人： Gareth Hougham ,  Leena Paivikki Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelorme ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

IPC分类号： B05D3/12 ,  B05D1/42

CPC分类号： H05K3/4053 ,  B05D1/002 ,  H01L21/486 ,  H01L21/76898 ,  H05K2201/09509 ,  H05K2203/1554

摘要： The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

摘要翻译： 本公开总体上涉及半导体，集成电路，特别是但不限于，用于填充高纵横比通孔和沟槽的离心方法，其具有粉末，浆料，材料的悬浮液，以充当导电的结构 支撑或电子部件的保护构件。

公开(公告)号：US07932169B2

公开(公告)日：2011-04-26

申请号：US12587301

申请日：2009-10-05

申请人： Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valérie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K Srivastava ,  Michael J. Sullivan

发明人： Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valérie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K Srivastava ,  Michael J. Sullivan

IPC分类号： H01L21/44

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2224/13099

摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

摘要翻译： 一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层 无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。 一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

公开(公告)号：US20080157395A1

公开(公告)日：2008-07-03

申请号：US11616919

申请日：2006-12-28

申请人： Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valerie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K. Srivastava ,  Michael J. Sullivan

发明人： Luc Belanger ,  Stephen L. Buchwalter ,  Leena Paivikki Buchwalter ,  Ajay P. Giri ,  Jonathan H. Griffith ,  Donald W. Henderson ,  Sung Kwon Kang ,  Eric H. Laine ,  Christian Lavoie ,  Paul A. Lauro ,  Valerie Anne Oberson ,  Da-Yuan Shih ,  Kamalesh K. Srivastava ,  Michael J. Sullivan

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2224/13099

摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

摘要翻译： 一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层 无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。 一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

公开(公告)号：US07815968B2

公开(公告)日：2010-10-19

申请号：US12247894

申请日：2008-10-08

申请人： Gareth Hougham ,  Leena Paivikki Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelmore ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

发明人： Gareth Hougham ,  Leena Paivikki Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelmore ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

IPC分类号： B05D3/12

CPC分类号： H05K3/4053 ,  B05D1/002 ,  H01L21/486 ,  H01L21/76898 ,  H05K2201/09509 ,  H05K2203/1554

摘要： The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

摘要翻译： 本公开一般涉及半导体，集成电路，特别是但不限于，用于填充高纵横比通孔和沟槽的离心方法，其具有粉末，糊料，材料悬浮液，用作导电，结构 支撑或电子部件的保护构件。

公开(公告)号：US06924171B2

公开(公告)日：2005-08-02

申请号：US09782494

申请日：2001-02-13

申请人： Stephen L. Buchwalter ,  David Danovitch ,  Fuad Elias Doany ,  Claudius Feger ,  Peter A. Gruber ,  Revathi Iyengar ,  Nancy C. LaBianca

发明人： Stephen L. Buchwalter ,  David Danovitch ,  Fuad Elias Doany ,  Claudius Feger ,  Peter A. Gruber ,  Revathi Iyengar ,  Nancy C. LaBianca

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/29 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/27 ,  H01L21/563 ,  H01L23/295 ,  H01L24/11 ,  H01L24/29 ,  H01L24/94 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/01083 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05599

摘要： Methods for fabricating microelectronic interconnection structures as well as the structures formed by the methods are disclosed which improve the manufacturing throughput for assembling flip chip semiconductor devices. The use of a bilayer of polymeric materials applied on the wafer prior to dicing eliminates the need for dispensing and curing underfill for each semiconductor at the package level, thereby improving manufacturing throughput and reducing cost.

摘要翻译： 公开了制造微电子互连结构的方法以及通过这些方法形成的结构，其提高了组装倒装芯片半导体器件的制造吞吐量。 在切割之前使用在晶片上施加的聚合物材料的双层，消除了在封装级别为每个半导体分配和固化底部填充物的需要，从而提高制造产量并降低成本。

公开(公告)号：US20090032962A1

公开(公告)日：2009-02-05

申请号：US12247894

申请日：2008-10-08

申请人： Gareth Hougham ,  Leena P. Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelorme ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

发明人： Gareth Hougham ,  Leena P. Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelorme ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

IPC分类号： H01L23/52 ,  H01L21/44 ,  B04B11/00

CPC分类号： H05K3/4053 ,  B05D1/002 ,  H01L21/486 ,  H01L21/76898 ,  H05K2201/09509 ,  H05K2203/1554

摘要： The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

摘要翻译： 本公开一般涉及半导体，集成电路，特别是但不限于，用于填充高纵横比通孔和沟槽的离心方法，其具有粉末，糊料，材料悬浮液，用作导电，结构 支撑或电子部件的保护构件。

公开(公告)号：US20090181476A1

公开(公告)日：2009-07-16

申请号：US11972129

申请日：2008-01-10

申请人： Stephen L. Buchwalter ,  Bing Dang ,  Claudius Feger ,  Peter A. Gruber ,  John Knickerbocker

发明人： Stephen L. Buchwalter ,  Bing Dang ,  Claudius Feger ,  Peter A. Gruber ,  John Knickerbocker

IPC分类号： H01L21/02

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of stacking a chip, including an integrated circuit, onto a substrate including applying an anisotropic conductive film (ACF) or a solder-filled conductive film onto a surface thereof, the surface being configured to electrically couple to the film, placing the chip onto the film, the chip being configured to electrically couple to the film, compressively pressurizing the chip, the film and the surface such that the chip is electrically coupled to the surface via the film,, testing the chip to determine whether the chip is operating normally, reworking the placement of the chip onto the film and repeating the compressive pressurization if the chip is determined to not be operating normally, repeating the testing to determine whether the chip is operating normally, and once the chip is determined to be operating normally, bonding the chip, the film and the surface.

摘要翻译： 一种将包括集成电路的芯片堆叠在基板上的方法，包括将各向异性导电膜（ACF）或焊料填充导电膜施加到其表面上，该表面被配置为电耦合到膜，将芯片 芯片被配置为电耦合到膜，对芯片，膜和表面进行压缩加压，使得芯片经由膜电耦合到表面，测试芯片以确定芯片是否正在操作 通常，如果芯片被确定为不正常工作，重复测试以确定芯片是否正常工作，并且一旦芯片确定正常工作，则将芯片放置在膜上并重复压缩加压， 粘合芯片，薄膜和表面。