公开(公告)号：US20060014331A1

公开(公告)日：2006-01-19

申请号：US10879480

申请日：2004-06-30

申请人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

发明人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841

摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

摘要翻译： 浮体动态随机存取存储器件可以包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。 可以在半导体主体的顶表面和半导体本体的横向相对的侧壁上形成栅介质层。 栅极电极可以形成在半导体本体的顶表面上的栅极电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。 栅电极可能仅部分地耗尽半导体本体的区域，并且部分耗尽的区域可以用作逻辑状态的存储节点。

公开(公告)号：US20060267093A1

公开(公告)日：2006-11-30

申请号：US11429490

申请日：2006-05-04

申请人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

发明人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841

摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

公开(公告)号：US20060054977A1

公开(公告)日：2006-03-16

申请号：US10942019

申请日：2004-09-16

申请人： Dinesh Somasekhar ,  Shekhar Borkar ,  Vivek De ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu

发明人： Dinesh Somasekhar ,  Shekhar Borkar ,  Vivek De ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C11/404 ,  G11C16/0416

摘要： A memory device is provided that includes a plurality of memory cells where each memory cell includes a source region, a drain region and a floating gate. A coupling bit-line is also provided that extends over at least one column of the plurality of memory cells. The coupling bit-line may be formed on each of the floating gates of memory cells forming the column of the plurality of memory cells. The coupling bit-line may also be formed within a well of each of memory cells forming the column of the plurality of memory cells.

摘要翻译： 提供一种存储器件，其包括多个存储器单元，其中每个存储器单元包括源极区域，漏极区域和浮动栅极。 还提供了在多个存储单元中的至少一列延伸的耦合位线。 耦合位线可以形成在形成多个存储单元的列的存储单元的每个浮置栅极上。 耦合位线也可以形成在形成多个存储器单元的列的每个存储单元的阱中。

公开(公告)号：US20050145886A1

公开(公告)日：2005-07-07

申请号：US10750572

申请日：2003-12-31

申请人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

发明人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC分类号： G11C11/404 ,  H01L21/8239 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

摘要翻译： 一些实施例提供了包括体区，源区和漏区的存储单元。 主体区域掺杂有第一类型的电荷载流子，源极区域设置在体区中并掺杂有第二类型的电荷载流子，并且漏极区域设置在体区中并掺杂有第二类型的载流子 类型。 主体区域和源极区域形成第一结，主体区域和漏极区域形成第二结，并且在第一接合点不偏向的情况下，从体区域到源极区域的第一结的导电率基本上 在第二接头不偏差的情况下，小于从体区到漏区的第二结的导电性。

公开(公告)号：US20050135169A1

公开(公告)日：2005-06-23

申请号：US10740551

申请日：2003-12-22

申请人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

发明人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

IPC分类号： G11C7/14 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4099 ,  G11C7/02

CPC分类号： G11C11/4099 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4097

摘要： An apparatus and method for generating a reference in a memory circuit are disclosed. At least two dummy bit-cells are used to generate a reference voltage. One cell has high value stored and the other has a low value stored. The cells are activated and discharged into respective bit-lines. The bit-lines are equalized during the discharge process to generate a reference that is approximately a mid point between a high value cell and a low value cell.

摘要翻译： 公开了一种用于在存储器电路中产生参考的装置和方法。 使用至少两个伪位单元来产生参考电压。 一个单元格具有高存储值，另一个存储值较低。 电池被激活并放电到相应的位线。 在放电过程期间，位线被均衡以产生大约高值单元和低值单元之间的中点的参考。

公开(公告)号：US20060054933A1

公开(公告)日：2006-03-16

申请号：US11268098

申请日：2005-11-07

申请人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

发明人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC分类号： H01L27/10

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

公开(公告)号：US20060002211A1

公开(公告)日：2006-01-05

申请号：US10881001

申请日：2004-06-30

申请人： Yibin Ye ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

发明人： Yibin Ye ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

IPC分类号： G11C7/00

CPC分类号： G11C11/405

摘要： A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.

公开(公告)号：US20050146956A1

公开(公告)日：2005-07-07

申请号：US10746148

申请日：2003-12-24

申请人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

发明人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

IPC分类号： G11C7/00 ,  G11C7/12

CPC分类号： G11C7/12

摘要： Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.

摘要翻译： 一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电， 使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。 此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。

公开(公告)号：US20050111255A1

公开(公告)日：2005-05-26

申请号：US10721184

申请日：2003-11-26

申请人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

发明人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC分类号： G11C11/404 ,  H01L27/108 ,  G11C11/34

CPC分类号： H01L27/108 ,  G11C11/404

摘要： Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

摘要翻译： 实施例涉及浮体动态随机存取存储器（FBDRAM）。 在将数据写入FBDRAM单元之前，FBDRAM利用清除线来复位FBDRAM单元。

公开(公告)号：US20060067126A1

公开(公告)日：2006-03-30

申请号：US10954931

申请日：2004-09-30

申请人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

发明人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/12 ,  G11C11/4076 ,  G11C2216/14

摘要： A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the word line. Some embodiments provide biasing of one or more of the plurality of memory cells in saturation to inject charge carriers into the body of the one or more of the plurality of memory cells, and biasing of each of the plurality of memory cells in accumulation to tunnel charge carriers from the body of each of the plurality of memory cells to the gate of each of the plurality of memory cells.