公开(公告)号：US20120037998A1

公开(公告)日：2012-02-16

申请号：US12855738

申请日：2010-08-13

申请人： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L27/092 ,  H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

摘要： A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.

摘要翻译： 形成具有压应力通道的p型场效应晶体管（PFET）和具有拉伸应力通道的n型场效应晶体管（NFET）。 在一个实施例中，使用硅 - 锗合金作为器件层，并且使用嵌入的含锗区域形成PFET的源极和漏极区域，并且使用嵌入的含硅区域形成NFET的源极和漏极区域 。 在另一个实施例中，锗层用作器件层，PFET的源极和漏极区通过将原子半径大于锗的原子半径的IIIA族元素注入到锗层的部分中而形成， 使用嵌入式硅 - 锗合金区域形成NFET的源极和漏极区域。 压应力和拉伸应力分别提高了PFET和NFET中载流子的迁移率。

公开(公告)号：US08354694B2

公开(公告)日：2013-01-15

申请号：US12855738

申请日：2010-08-13

申请人： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

摘要： A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.

摘要翻译： 形成具有压应力通道的p型场效应晶体管（PFET）和具有拉伸应力通道的n型场效应晶体管（NFET）。 在一个实施例中，使用硅 - 锗合金作为器件层，并且使用嵌入的含锗区域形成PFET的源极和漏极区域，并且使用嵌入的含硅区域形成NFET的源极和漏极区域 。 在另一个实施例中，锗层用作器件层，PFET的源极和漏极区通过将原子半径大于锗的原子半径的IIIA族元素注入到锗层的部分中而形成， 使用嵌入式硅 - 锗合金区域形成NFET的源极和漏极区域。 压应力和拉伸应力分别提高了PFET和NFET中载流子的迁移率。

公开(公告)号：US20120031476A1

公开(公告)日：2012-02-09

申请号：US12849966

申请日：2010-08-04

申请人： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L31/0352 ,  H01L31/18

CPC分类号： H01L31/065 ,  H01L31/03765 ,  H01L31/075 ,  H01L31/18 ,  Y02E10/548

摘要： A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device.

摘要翻译： 光伏器件包括组成调制的半导体结构，其包括p掺杂的第一半导体材料层，第一本征成分梯度半导体材料层，本征半导体材料层，第二本征组分梯度半导体层和n掺杂的第一半导体层 半导体材料层。 第一和第二本征成分梯度半导体材料层包括具有较大带隙宽度的第一半导体材料和具有较小带隙的第二半导体材料的合金，并且第二半导体材料的浓度朝向本征半导体 第一和第二组成梯度半导体材料层中的材料层。 光电器件提供与第一半导体材料相当的开路电压，以及与第二半导体材料相当的短路电流，从而提高光伏器件的效率。

公开(公告)号：US08653360B2

公开(公告)日：2014-02-18

申请号：US12849966

申请日：2010-08-04

申请人： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01L31/065 ,  H01L31/03765 ,  H01L31/075 ,  H01L31/18 ,  Y02E10/548

摘要： A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device.

摘要翻译： 光伏器件包括组成调制的半导体结构，其包括p掺杂的第一半导体材料层，第一本征成分梯度半导体材料层，本征半导体材料层，第二本征组分梯度半导体层和n掺杂的第一半导体层 半导体材料层。 第一和第二本征成分梯度半导体材料层包括具有较大带隙宽度的第一半导体材料和具有较小带隙的第二半导体材料的合金，并且第二半导体材料的浓度朝向本征半导体 第一和第二组成梯度半导体材料层中的材料层。 光电器件提供与第一半导体材料相当的开路电压，以及与第二半导体材料相当的短路电流，从而提高光伏器件的效率。

公开(公告)号：US08866227B2

公开(公告)日：2014-10-21

申请号：US13607743

申请日：2012-09-09

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/77 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域 以及掺杂有碳层的硅的第三器件区域。 然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。 可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。 可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。

公开(公告)号：US20130099319A1

公开(公告)日：2013-04-25

申请号：US13607743

申请日：2012-09-09

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域 以及掺杂有碳层的硅的第三器件区域。 然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。 可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。 可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。

公开(公告)号：US20130099318A1

公开(公告)日：2013-04-25

申请号：US13280850

申请日：2011-10-25

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/092 ,  H01L21/20

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

公开(公告)号：US20120295417A1

公开(公告)日：2012-11-22

申请号：US13109567

申请日：2011-05-17

申请人： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

发明人： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

IPC分类号： H01L21/20

CPC分类号： H01L29/66628 ,  H01L21/0237 ,  H01L21/02524 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/78

摘要： A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.

摘要翻译： 提供了一种控制外延生长室中不同材料的成核速率（即孵育时间）的方法，其可以有利于高生长速率并且可以与低温生长相容。 通过选择具有给定的天然成核特性的合适的掩蔽材料，通过相对于相同材料膜的单晶生长改变给定材料膜的生长的成核速率，在外延生长室中控制不同材料的成核速率 ，或通过改变掩模层的表面以获得适当的成核特性。 或者，可以通过相对于其后将形成外延半导体材料的其它区域修改半导体衬底的选定区域的表面来实现成核速率控制。

公开(公告)号：US20120205784A1

公开(公告)日：2012-08-16

申请号：US13037944

申请日：2011-03-01

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L29/02 ,  H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

摘要： Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient.

摘要翻译： 使用氢将压缩应变硅在低温下直接外延生长到硅衬底上以设计应变水平。 在这样的生长过程中氢稀释可以变化以提供应变梯度。

公开(公告)号：US20090134460A1

公开(公告)日：2009-05-28

申请号：US12363239

申请日：2009-01-30

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/00 ,  H01L21/71

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。