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    Method of forming a silicon nitride layer on a substrate
    1.
    发明授权
    Method of forming a silicon nitride layer on a substrate 有权
    在基板上形成氮化硅层的方法

    公开(公告)号：US06559074B1

    公开(公告)日：2003-05-06

    申请号：US10015713

    申请日：2001-12-12

    申请人： Steven A. Chen ,  Xianzhi Tao ,  Shulin Wang ,  Lee Luo ,  Kegang Huang ,  Sang H. Ahn

    发明人： Steven A. Chen ,  Xianzhi Tao ,  Shulin Wang ,  Lee Luo ,  Kegang Huang ,  Sang H. Ahn

    IPC分类号： H01L2131

    CPC分类号： C23C16/345 ,  H01L21/3185 ,  Y10S438/958

    摘要： A silicon nitride layer is formed over transistor gates while the processing temperature is relatively high, typically at least 500° C., and the pressure is relatively high, typically at least 50 Torr, to obtain a relatively high rate of formation of the silicon nitride layer. Processing conditions are controlled so as to more uniformly form the silicon nitride layer. Generally, the ratio of the NH3 gas to the silicon-containing gas by volume is selected sufficiently high so that, should the surface have a low region between transistor gates which is less than 0.15 microns wide and have a height-to-width ratio of at least 1.0, as well as an entirely flat area of at least 5 microns by 5 microns, the layer forms at a rate of not more than 25% faster on the flat area than on a base of the low region.

    摘要翻译： 在晶体管栅极上形成氮化硅层，而处理温度相对较高，通常至少为500℃，压力相对较高，通常为至少50托，以获得较高的氮化硅形成速率 层。 控制处理条件以更均匀地形成氮化硅层。 通常，体积的NH 3气体与含硅气体的比例被选择得足够高，使得如果表面在小于0.15微米宽的晶体管栅极之间具有低区域，并且具有高度 - 宽度比 至少为1.0，以及至少5微米至5微米的完全平坦的区域，该层在平坦区域上比在低区域的基底上以不超过25％的速率形成。

    Doped silicon deposition process in resistively heated single wafer chamber
    3.
    发明授权
    Doped silicon deposition process in resistively heated single wafer chamber 有权
    在电阻加热的单晶片室中掺杂硅沉积工艺

    公开(公告)号：US06559039B2

    公开(公告)日：2003-05-06

    申请号：US09858821

    申请日：2001-05-15

    申请人： Shulin Wang ,  Lee Luo ,  Steven A. Chen ,  Errol Sanchez ,  Xianzhi Tao ,  Zoran Dragojlovic ,  Li Fu

    发明人： Shulin Wang ,  Lee Luo ,  Steven A. Chen ,  Errol Sanchez ,  Xianzhi Tao ,  Zoran Dragojlovic ,  Li Fu

    IPC分类号： H01L2124

    CPC分类号： H01L21/67103 ,  C23C16/24 ,  C23C16/45557 ,  C23C16/4586 ,  C23C16/46 ,  H01L21/28556 ,  H01L21/76877

    摘要： A method for depositing doped polycrystalline or amorphous silicon film. The method includes placing a substrate onto a susceptor. The susceptor includes a body having a resistive heater therein and a thermocouple in physical contact with the resistive heater. The susceptor is located in the process chamber such that the process chamber has a top portion above the susceptor and a bottom portion below the susceptor. The method further includes heating the susceptor. The method further includes providing a process gas mix into the process chamber through a shower head located on the susceptor. The process gas mix includes a silicon source gas, a dopant gas, and a carrier gas. The carrier gas includes nitrogen. The method further includes forming the doped silicon film from the silicon source gas.

    摘要翻译： 一种沉积掺杂多晶或非晶硅膜的方法。 该方法包括将基底放置在基座上。 感受体包括其中具有电阻加热器的主体和与电阻加热器物理接触的热电偶。 感受体位于处理室中，使得处理室具有在基座上方的顶部部分和基座下方的底部部分。 该方法还包括加热基座。 该方法还包括通过位于基座上的喷淋头将工艺气体混合物提供到处理室中。 处理气体混合物包括硅源气体，掺杂剂气体和载气。 载气包括氮气。 该方法还包括从硅源气体形成掺杂硅膜。

    Method of making a transistor, in particular spacers of the transistor
    6.
    发明授权
    Method of making a transistor, in particular spacers of the transistor 失效
    制造晶体管的方法，特别是晶体管的间隔物

    公开(公告)号：US06566183B1

    公开(公告)日：2003-05-20

    申请号：US10017192

    申请日：2001-12-12

    申请人： Steven A. Chen ,  Lee Luo ,  Kegang Huang ,  Tzy-Tzan Fu ,  Kuan-Ting Lin ,  Hung-Chuan Chen

    发明人： Steven A. Chen ,  Lee Luo ,  Kegang Huang ,  Tzy-Tzan Fu ,  Kuan-Ting Lin ,  Hung-Chuan Chen

    IPC分类号： H01L218238

    CPC分类号： H01L29/6659 ,  H01L21/3185 ,  H01L29/6656 ,  H01L29/7833

    摘要： The invention provides a method of making a transistor. A gate dielectric layer is formed on a semiconductor substrate. A gate is formed on the dielectric layer, the gate having an exposed upper surface and exposed side surfaces. A first silicon nitride layer having a first thickness is deposited over the gate, for example over an oxide layer on the gate, at a first deposition rate. A second silicon nitride layer having a second thickness is deposited over the first silicon nitride layer at a second deposition rate, the second thickness being more that the first thickness and the second deposition rate being more than the first deposition rate. The first silicon nitrogen layer then has a lower hydrogen concentration. At least the second silicon nitride layer (or a silicon oxide layer in the case of an ONO spacer) is etched to leave spacers next to the side surfaces while exposing the upper surface of the gate and areas of the substrate outside the spacers.

    摘要翻译： 本发明提供一种制造晶体管的方法。 在半导体衬底上形成栅介电层。 栅极形成在电介质层上，栅极具有暴露的上表面和暴露的侧表面。 具有第一厚度的第一氮化硅层以第一沉积速率沉积在栅极上，例如在栅极上的氧化物层上方。 具有第二厚度的第二氮化硅层以第二沉积速率沉积在第一氮化硅层上，第二厚度大于第一厚度和第二沉积速率大于第一沉积速率。 然后第一硅氮层具有较低的氢浓度。 蚀刻至少第二氮化硅层（或在ONO间隔物的情况下的氧化硅层），以使隔板靠近侧表面，同时将栅极的上表面和衬底的区域暴露在间隔物外部。

    TUNGSTEN NITRIDE ATOMIC LAYER DEPOSITION PROCESSES
    10.
    发明申请
    TUNGSTEN NITRIDE ATOMIC LAYER DEPOSITION PROCESSES 有权
    TINGSTEN NITRIDE原子层沉积法

    公开(公告)号：US20070020924A1

    公开(公告)日：2007-01-25

    申请号：US11532114

    申请日：2006-09-15

    申请人： Shulin Wang ,  Ulrich Kroemer ,  Lee Luo ,  Aihua Chen ,  Ming Li

    发明人： Shulin Wang ,  Ulrich Kroemer ,  Lee Luo ,  Aihua Chen ,  Ming Li

    IPC分类号： H01L21/4763

    CPC分类号： C23C16/45527 ,  C23C16/02 ,  C23C16/34 ,  C23C16/45525 ,  H01L21/28061 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76841 ,  H01L27/10861 ,  H01L28/60 ,  H01L29/4941 ,  H01L29/66181

    摘要： In one embodiment, a method for forming a tungsten barrier material on a substrate is provided which includes depositing a tungsten layer on a substrate during a vapor deposition process and exposing the substrate sequentially to a tungsten precursor and a nitrogen precursor to form a tungsten nitride layer on the tungsten layer. Some examples provide that the tungsten layer may be deposited by sequentially exposing the substrate to the tungsten precursor and a reducing gas (e.g., diborane or silane) during an atomic layer deposition process. The tungsten layer may have a thickness of about 50 Å or less and tungsten nitride layer may have an electrical resistivity of about 380 μΩ-cm or less. Other examples provide that a tungsten bulk layer may be deposited on the tungsten nitride layer by a chemical vapor deposition process.

    摘要翻译： 在一个实施例中，提供了一种在衬底上形成钨阻挡材料的方法，其包括在气相沉积工艺期间在衬底上沉积钨层并将衬底依次暴露于钨前体和氮前体以形成氮化钨层 在钨层上。 一些实施例提供可以在原子层沉积工艺期间通过依次将基底暴露于钨前体和还原气体（例如乙硼烷或硅烷）来沉积钨层。 钨层的厚度可以为约或者更小，并且氮化钨层的电阻率可以为约380μΩ·cm以下。 其它实例提供了通过化学气相沉积工艺在钨氮化物层上沉积钨体层。