公开(公告)号：US5728222A

公开(公告)日：1998-03-17

申请号：US541278

申请日：1995-10-12

申请人： Steven George Barbee ,  Richard Anthony Conti ,  Alexander Kostenko ,  Narayana V. Sarma ,  Donald Leslie Wilson ,  Justin Wai-Chow Wong ,  Steven Paul Zuhoski

发明人： Steven George Barbee ,  Richard Anthony Conti ,  Alexander Kostenko ,  Narayana V. Sarma ,  Donald Leslie Wilson ,  Justin Wai-Chow Wong ,  Steven Paul Zuhoski

IPC分类号： C23C16/40 ,  C23C16/46 ,  C23C16/52 ,  H01L21/205 ,  H01L21/31 ,  B05C11/00

CPC分类号： C23C16/403 ,  C23C16/46 ,  C23C16/52

摘要： An apparatus in a chemical vapor deposition (CVD) system monitors the actual wafer/substrate temperature during the deposition process. The apparatus makes possible the production of high quality aluminum oxide films with real-time wafer/substrate control. An infrared (IR) temperature monitoring device is used to control the actual wafer temperature to the process temperature setpoint. This eliminates all atmospheric temperature probing. The need for test runs and monitor wafers as well as the resources required to perform the operations is eliminated and operating cost are reduced. High quality, uniform films of aluminum oxide can be deposited on a silicon substrates with no need for additional photolithographic steps to simulate conformality that are present in a sputtered (PVD) type application. The result is a reduction in required process steps with subsequent anticipated savings in equipment, cycle time, chemicals, reduce handling, and increased yield of devices on the substrate. The apparatus incorporates a heated source material, heated delivery lines, heated inert gas purge lines, a pressure differential mass flow controller, a control system with related valving, and a vacuum process chamber with walls that are temperature controlled as a complete source delivery system to accurately and repeatably provide source vapor for LPCVD deposition of aluminum oxide onto silicon substrates.

摘要翻译： 化学气相沉积（CVD）系统中的装置在沉积过程中监测实际的晶片/衬底温度。 该设备使得可以生产具有实时晶片/衬底控制的高品质氧化铝膜。 使用红外（IR）温度监测装置将实际晶片温度控制到过程温度设定值。 这消除了所有的大气温度探测。 测试运行和监视晶圆以及执行操作所需的资源的需求被消除，运行成本降低。 可以在硅衬底上沉积高质量均匀的氧化铝膜，而不需要额外的光刻步骤来模拟存在于溅射（PVD）型应用中的共形性。 结果是所需的工艺步骤减少，随后预期节省设备，循环时间，化学品，减少处理和提高基材上装置的产量。 该装置包括加热的源材料，加热的输送管线，加热的惰性气体吹扫管线，压差质量流量控制器，具有相关阀门的控制系统和具有作为完整源输送系统温度控制的壁的真空处理室 准确并重复地提供源蒸气，用于LPCVD在硅衬底上沉积氧化铝。

公开(公告)号：US5648113A

公开(公告)日：1997-07-15

申请号：US316311

申请日：1994-09-30

申请人： Steven George Barbee ,  Jonathan Daniel Chapple-Sokol ,  Richard Anthony Conti ,  Richard Hsiao ,  James Anthony O'Neill ,  Narayana V. Sarma ,  Donald Leslie Wilson ,  Justin Wai-Chow Wong ,  Steven Paul Zuhoski

发明人： Steven George Barbee ,  Jonathan Daniel Chapple-Sokol ,  Richard Anthony Conti ,  Richard Hsiao ,  James Anthony O'Neill ,  Narayana V. Sarma ,  Donald Leslie Wilson ,  Justin Wai-Chow Wong ,  Steven Paul Zuhoski

IPC分类号： C23C16/40 ,  C23C16/448 ,  C23C16/52 ,  H01L21/205 ,  H01L21/31 ,  H01L21/316

CPC分类号： C23C16/403 ,  C23C16/4481 ,  C23C16/52

摘要： A process and apparatus for Al.sub.2 O.sub.3 CVD on silicon wafers using aluminum tri-isopropoxide in a high-volume production environment is presented. The conditions required to use ATI in a production environment and provide maximum utilization of ATI are first of all delivery of ATI via direct evaporation. The ATI source bottle is pumped out (bypassing substrates) until propene and isopropanol signals are reduced to 1% of process pressure before start of aluminum oxide deposition. Either IR spectroscopy or mass spectrometry can be used to provide a control signal to the microprocessor controller. Heating the supplied tetramer to 120.degree. C. for two hours assures complete conversion to trimer. The ATI is stored at 90.degree. C. to minimize decomposition during idle periods and allow recovery of trimer upon return to 120.degree. C. for two hours. During periods of demand, the ATI is held at 120.degree. C. to minimize decomposition.

摘要翻译： 提出了一种用于在大量生产环境中使用三异丙氧基铝的硅晶片上的Al 2 O 3 CVD的工艺和装置。 在生产环境中使用ATI并提供ATI的最大利用率所需的条件首先通过直接蒸发传送ATI。 在开始氧化铝沉积之前，将ATI源瓶泵出（旁路基板），直到丙烯和异丙醇信号降低到过程压力的1％。 可以使用IR光谱或质谱法向微处理器控制器提供控制信号。 将供应的四聚体加热至120℃保持两小时，确保完全转化为三聚体。 将ATI储存在90℃以使空闲期间的分解最小化，并允许在回到120℃回收三聚体两小时。 在需求期间，ATI保持在120℃以最小化分解。

公开(公告)号：US5665608A

公开(公告)日：1997-09-09

申请号：US386403

申请日：1995-02-10

申请人： Jonathan Daniel Chapple-Sokol ,  Richard Anthony Conti ,  James Anthony O'Neill ,  Narayana V. Sarma ,  Donald Leslie Wilson ,  Justin Wai-Chow Wong

发明人： Jonathan Daniel Chapple-Sokol ,  Richard Anthony Conti ,  James Anthony O'Neill ,  Narayana V. Sarma ,  Donald Leslie Wilson ,  Justin Wai-Chow Wong

IPC分类号： H01L21/205 ,  C23C16/40 ,  C23C16/44 ,  C23C16/448 ,  C23C16/52 ,  H01L21/66

CPC分类号： C23C16/52 ,  C23C16/403 ,  C23C16/4402 ,  C23C16/4485 ,  Y10S438/935

摘要： A method and apparatus for monitoring and controlling reactant vapors prior to chemical vapor deposition (CVD). The reactant vapors are monitored at full concentration without sampling as they are transported to a CVD reactor. Contaminants detected cause a process controller to switch the transport path to direct reactant vapors to a system pump.

摘要翻译： 一种用于在化学气相沉积（CVD）之前监测和控制反应物蒸气的方法和装置。 当反应物蒸气被输送到CVD反应器时，反应物蒸气以全浓度监测，不进行取样。 检测到的污染物导致过程控制器将输送路径切换为直接反应物蒸汽到系统泵。

公开(公告)号：US6114736A

公开(公告)日：2000-09-05

申请号：US351808

申请日：1999-07-12

申请人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

发明人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L23/283

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656 ,  H01L2924/0002 ,  Y10S257/916

摘要： A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

摘要翻译： 在其上形成有N阱的P掺杂半导体衬底上形成MOSFET器件，在N阱中形成一对隔离区，其中形成在N阱上方的栅氧化层。 FET器件在N阱内形成有源极和漏极区，以及形成在栅极氧化物层上方的与栅极和漏极区对准的栅电极。 栅电极包括一叠层。 在栅氧化层上形成多晶硅层。 在具有约5nm至约20nm的厚度的多晶硅层上形成氮化钨掺杂剂阻挡层，并且在氮化钨层上形成硅化钨层。

公开(公告)号：US20080233709A1

公开(公告)日：2008-09-25

申请号：US11689884

申请日：2007-03-22

申请人： Richard Anthony Conti ,  Armin T. Tilke ,  Chris Stapelmann ,  Michael R. Sievers

发明人： Richard Anthony Conti ,  Armin T. Tilke ,  Chris Stapelmann ,  Michael R. Sievers

IPC分类号： H01L21/762 ,  H01L21/311

CPC分类号： H01L21/31111 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76229

摘要： A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time of the film on the surface of the material to etch at least a portion of the material, and removing any unwanted reactant and reaction product from the chamber or the surface of the material.

摘要翻译： 一种用于从半导体中的沟槽中去除材料的方法。 该方法包括将半导体放置在真空室中，在反应物的压力下将反应物导入到腔室中以在材料的表面上形成反应物的膜，从而控制膜在材料表面上的组成和停留时间 蚀刻材料的至少一部分，并从室或材料表面去除任何不需要的反应物和反应产物。

公开(公告)号：US5923999A

公开(公告)日：1999-07-13

申请号：US741159

申请日：1996-10-29

申请人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

发明人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656 ,  H01L2924/0002 ,  Y10S257/916

摘要： A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

摘要翻译： 在其上形成有N阱的P掺杂半导体衬底上形成MOSFET器件，在N阱中形成一对隔离区，其中形成在N阱上方的栅氧化层。 FET器件在N阱内形成有源极和漏极区，以及形成在栅极氧化物层上方的与栅极和漏极区对准的栅电极。 栅电极包括一叠层。 在栅氧化层上形成多晶硅层。 在具有约5nm至约20nm的厚度的多晶硅层上形成氮化钨掺杂剂阻挡层，并且在氮化钨层上形成硅化钨层。

公开(公告)号：US07838390B2

公开(公告)日：2010-11-23

申请号：US11871602

申请日：2007-10-12

申请人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

发明人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

IPC分类号： H01L21/76

CPC分类号： H01L21/3105 ,  H01L21/76229 ,  H01L21/76232

摘要： Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面中形成沟槽，并用其中具有接缝的电绝缘区填充沟槽。 可以通过在沟槽的侧壁和底部上沉积足够厚的电绝缘层来填充沟槽。 然后将固化离子以足够的能量和剂量注入电绝缘区域以减少其中原子序列的程度。 固化离子可以是选自氮（N），磷（P），硼（B），砷（As），碳（C），氩（Ar），锗（Ge），氦 ），氖（Ne）和氙（Xe）。 这些固化离子可以以至少约80KeV的能量和至少约5×10 14离子/ cm 2的剂量注入。 然后将电绝缘区域在足够的温度下退火并持续足够的时间以增加电绝缘区域内的原子级数。

公开(公告)号：US6049131A

公开(公告)日：2000-04-11

申请号：US887786

申请日：1997-07-03

申请人： Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Seshadri Subbanna

发明人： Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Seshadri Subbanna

IPC分类号： C23C16/04 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/76897 ,  C23C16/04 ,  H01L21/28061 ,  H01L21/28562 ,  H01L29/66515

摘要： A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g., worm holes), poor adhesion, uncontrolled selectivity and uneven morphology.

摘要翻译： 公开了通过在暴露的硅上而不是场氧化物上的选择性难熔金属生长/沉积的方法制备的方法和装置。 该方法包括在DHF浸渍中预处理晶片，随后是以下步骤：1）通过使难熔金属卤化物与所述硅衬底的暴露表面反应来选择性地将难熔金属沉积在硅衬底的暴露表面上; 2）通过使难熔金属卤化物与含硅气体反应来限制硅衬底的消耗; 和3）通过使难熔金属卤化物与氢反应来进一步增加难熔金属厚度。 通过适当的预处理和选择参数1）温度; 2）压力; 3）时间; 4）流程和5）每个沉积步骤中的流量比，本发明充分地解决了不均匀的n +与p +（源/漏）生长，难熔金属深入/侵入硅区域（例如蠕虫孔）的困难， 粘附性差，不受控制的选择性和不均匀的形态。

公开(公告)号：US20090098706A1

公开(公告)日：2009-04-16

申请号：US11871602

申请日：2007-10-12

申请人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

发明人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

IPC分类号： H01L21/762

CPC分类号： H01L21/3105 ,  H01L21/76229 ,  H01L21/76232

摘要： Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面中形成沟槽，并用其中具有接缝的电绝缘区填充沟槽。 可以通过在沟槽的侧壁和底部上沉积足够厚的电绝缘层来填充沟槽。 然后将固化离子以足够的能量和剂量注入电绝缘区域以减少其中原子序列的程度。 固化离子可以是选自氮（N），磷（P），硼（B），砷（As），碳（C），氩（Ar），锗（Ge），氦 ），氖（Ne）和氙（Xe）。 这些固化离子可以以至少约80KeV的能量和至少约5×1014个离子/ cm 2的剂量注入。 然后将电绝缘区域在足够的温度下退火并持续足够的时间以增加电绝缘区域内的原子级数。

公开(公告)号：US5807788A

公开(公告)日：1998-09-15

申请号：US753128

申请日：1996-11-20

申请人： Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Seshadri Subbanna

发明人： Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Seshadri Subbanna

IPC分类号： C23C16/04 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L21/76897 ,  C23C16/04 ,  H01L21/28061 ,  H01L21/28562 ,  H01L29/66515

摘要： A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g., worm holes), poor adhesion, uncontrolled selectivity and uneven morphology.

摘要翻译： 公开了通过在暴露的硅上而不是场氧化物上的选择性难熔金属生长/沉积的方法制备的方法和装置。 该方法包括在DHF浸渍中预处理晶片，随后是以下步骤：1）通过使难熔金属卤化物与所述硅衬底的暴露表面反应来选择性地将难熔金属沉积在硅衬底的暴露表面上; 2）通过使难熔金属卤化物与含硅气体反应来限制硅衬底的消耗; 和3）通过使难熔金属卤化物与氢反应来进一步增加难熔金属厚度。 通过适当的预处理和选择参数1）温度; 2）压力; 3）时间; 4）流程和5）每个沉积步骤中的流量比，本发明充分地解决了不均匀的n +与p +（源/漏）生长，难熔金属深入/侵入硅区域（例如蠕虫孔）的困难， 粘附性差，不受控制的选择性和不均匀的形态。