-
公开(公告)号：US07194671B2
公开(公告)日：2007-03-20
申请号：US10039587
申请日：2001-12-31
CPC分类号： G06F11/165 , G06F11/1641 , G06F11/1645
摘要： An processor includes first and second execution cores that operate in an FRC mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The FRC check unit temporarily stores results from the first or second core, and a timer is activated if a mismatch is detected. If the error detector detects a recoverable error before the timer interval expires, a recovery routine is activated. If the timer interval expires first, a reset routine is activated.
摘要翻译： 处理器包括以FRC模式操作的第一和第二执行核心，用于比较来自第一和第二执行核心的结果的FRC检查单元和用于检测第一和第二核心中的可恢复错误的错误检查单元。 FRC检查单元临时存储来自第一或第二核的结果，并且如果检测到不匹配，则定时器被激活。 如果错误检测器在定时器间隔到期之前检测到可恢复的错误，则激活恢复例程。 如果定时器间隔首先到期，则复位例程被激活。
-
2.发明授权Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput 有权用于在保持窥探吞吐量的同时为处理器提供低功率模式的方法和装置公开(公告)号：US07694080B2
公开(公告)日：2010-04-06
申请号：US11027649
申请日：2004-12-29
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A method and apparatus for providing a low power mode for a processor while maintaining snoop throughput are disclosed. In one embodiment, an apparatus includes a cache, a processor, and a frequency controller. The frequency controller is to operate the apparatus in a low power mode in which the operating frequency of the cache is higher than the operating frequency of the processor.
摘要翻译： 公开了一种用于在保持窥探吞吐量的同时为处理器提供低功率模式的方法和装置。 在一个实施例中，装置包括高速缓存，处理器和频率控制器。 频率控制器将以高功率模式操作该设备，其中高速缓存的工作频率高于处理器的工作频率。
-
公开(公告)号：US07120755B2
公开(公告)日：2006-10-10
申请号：US10039060
申请日：2002-01-02
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific embodiments are described, using write buffers, fill buffers, and multiplexers, respectively, to achieve the on-chip transfer of data between dedicated caches.
-
4.发明授权Parallel apparatus for high-speed, highly compressed LZ77 tokenization and Huffman encoding for deflate compression 有权并行装置，用于高速，高度压缩的LZ77标记和霍夫曼编码，用于放气压缩公开(公告)号：US08766827B1
公开(公告)日：2014-07-01
申请号：US13853286
申请日：2013-03-29
IPC分类号： H03M7/34
CPC分类号： H03M7/3084
摘要： Parallel compression is performed on an input data stream by processing circuitry. The processing circuitry includes hashing circuitry, match engines, pipeline circuitry and a match selector. The hashing circuitry identifies multiple locations in one or more history buffers for searching for a target data in the input data stream. The match engines perform multiple searches in parallel for the target data in the one or more history buffers. The pipeline circuitry performs pipelined searches for multiple sequential target data in the input data stream in consecutive clock cycles. Then the match selector selects a result from the multiple searches and pipelined searches to compress the input data stream.
摘要翻译： 通过处理电路在输入数据流上执行并行压缩。 处理电路包括散列电路，匹配引擎，流水线电路和匹配选择器。 散列电路识别一个或多个历史缓冲器中的多个位置，用于在输入数据流中搜索目标数据。 匹配引擎对一个或多个历史缓冲区中的目标数据并行执行多个搜索。 流水线电路在连续的时钟周期内对输入数据流中的多个连续目标数据进行流水线搜索。 然后，匹配选择器从多个搜索和流水线搜索中选择一个结果来压缩输入数据流。
-
5.发明申请公开(公告)号：US20120262312A1
公开(公告)日：2012-10-18
申请号：US13085295
申请日：2011-04-12
IPC分类号： H03M7/30
CPC分类号： H03M7/40
摘要： An embodiment may include first circuitry and second circuitry. The first circuitry may compress, at least in part, based at least in part upon a first set of statistics, input to produce first output exhibiting a first compression ratio. If the first compression ratio is less than a desired compression ratio, the second circuitry may compress, at least in part, based at least in part upon a second set of statistics, the first output to produce second output. The first set of statistics may be based, at least in part, after an initial compression, upon other data that has been previously compressed and is associated, at least in part, with the input. The second set of statistics may be based at least in part upon the input. Many alternatives, variations, and modifications are possible.
摘要翻译： 实施例可以包括第一电路和第二电路。 至少部分地，第一电路可以至少部分地基于第一组统计量来输入以产生呈现第一压缩比的第一输出。 如果第一压缩比小于期望的压缩比，则第二电路可以至少部分地至少部分地基于第二组统计压缩第一输出以产生第二输出。 至少部分地，第一组统计信息可以至少部分地基于在初始压缩之后，至少部分地与输入相关联的先前压缩并且被关联的其他数据。 第二组统计数字可能至少部分地基于输入。 许多替代方案，变化和修改是可能的。
-
公开(公告)号：US07032134B2
公开(公告)日：2006-04-18
申请号：US09818788
申请日：2001-03-28
申请人： Ayman G. Abdo , Cameron McNairy , Piyush Desai , Quinn W. Merrell
发明人： Ayman G. Abdo , Cameron McNairy , Piyush Desai , Quinn W. Merrell
IPC分类号： G06F11/22
摘要： A validation FUB is a hardware system within the agent that can place a computer system in a stress condition. A validation FUB may monitor transactions posted on an external bus and generate other transactions in response to the monitored transactions. The validation FUB may be a programmable element whose response may be defined by an external input. Accordingly, the validation FUB may test a wide variety of system events.
-
7.发明授权System and method for exclusively writing tag during write allocate requests 失效在写入分配请求期间专门写入标签的系统和方法
公开(公告)号：US5787469A
公开(公告)日：1998-07-28
申请号：US709164
申请日：1996-09-06
申请人： Quinn W. Merrell
发明人： Quinn W. Merrell
IPC分类号： G06F12/08
CPC分类号： G06F12/0897
摘要： Implemented within a computer system, a cache memory element having a cache hierarchy including a first level cache and at least a second level cache. In the event that a processor core requests a copy of a selected cache line and intends to modify contents of the selected cache line and the selected cache line cannot be supplied by the first or second level cache, tag information is solely written into the second level cache and higher level caches. This preserves databus bandwidth and enhances performance of the computer system.
摘要翻译： 在计算机系统内实现具有包括第一级高速缓存和至少第二级高速缓存的高速缓存层级的高速缓冲存储器元件。 在处理器核心请求所选高速缓存行的副本并且旨在修改所选高速缓存行的内容并且所选择的高速缓存行不能由第一或第二级高速缓存提供的情况下，标签信息被单独写入第二级 缓存和更高级别的缓存。 这保留了数据总线带宽并增强了计算机系统的性能。
-
8.发明授权公开(公告)号：US08373583B2
公开(公告)日：2013-02-12
申请号：US13085295
申请日：2011-04-12
IPC分类号： H03M7/34
CPC分类号： H03M7/40
摘要： An embodiment may include first circuitry and second circuitry. The first circuitry may compress, at least in part, based at least in part upon a first set of statistics, input to produce first output exhibiting a first compression ratio. If the first compression ratio is less than a desired compression ratio, the second circuitry may compress, at least in part, based at least in part upon a second set of statistics, the first output to produce second output. The first set of statistics may be based, at least in part, after an initial compression, upon other data that has been previously compressed and is associated, at least in part, with the input. The second set of statistics may be based at least in part upon the input. Many alternatives, variations, and modifications are possible.
摘要翻译： 实施例可以包括第一电路和第二电路。 至少部分地，第一电路可以至少部分地基于第一组统计量来输入以产生呈现第一压缩比的第一输出。 如果第一压缩比小于期望的压缩比，则第二电路可以至少部分地至少部分地基于第二组统计压缩第一输出以产生第二输出。 至少部分地，第一组统计信息可以至少部分地基于在初始压缩之后，至少部分地与输入相关联的先前压缩并且被关联的其他数据。 第二组统计数字可能至少部分地基于输入。 许多替代方案，变化和修改是可能的。
-
9.发明授权公开(公告)号：US07487398B2
公开(公告)日：2009-02-03
申请号：US11300423
申请日：2005-12-15
申请人： Ayman G. Abdo , Cameron McNairy , Piyush Desai , Quinn W. Merrell
发明人： Ayman G. Abdo , Cameron McNairy , Piyush Desai , Quinn W. Merrell
IPC分类号： G06F11/00
摘要： Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.
摘要翻译： 通过在总线上产生骚扰事务来测试计算机系统的元素。 在总线上检测到第一个事务。 第一个事务包括对第一个地址的第一个数据请求。 响应并且基于检测到第一地址，生成第二数据请求到第二地址。 第二个数据请求作为第二个事务在总线上发出，而总线上第一个事务处于待处理状态。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.024 秒)