公开(公告)号：US07337101B1

公开(公告)日：2008-02-26

申请号：US10417702

申请日：2003-04-17

申请人： Steven Perry ,  Gregor Nixon ,  Ziad Abu-Lebdeh ,  Alasdair Scott ,  Philippe Marti

发明人： Steven Perry ,  Gregor Nixon ,  Ziad Abu-Lebdeh ,  Alasdair Scott ,  Philippe Marti

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method for designing a system on a programmable logic device (PLD) includes translating a timing requirement of the system into a geographical constraint. Resources on the PLD are fitted onto locations on the PLD in response to the geographical constraint.

摘要翻译： 用于在可编程逻辑器件（PLD）上设计系统的方法包括将系统的定时要求转换为地理约束。 PLD上的资源适应于PLD的位置以响应地理约束。

公开(公告)号：US07216330B1

公开(公告)日：2007-05-08

申请号：US10413081

申请日：2003-04-14

申请人： Steven Perry ,  Gregor Nixon ,  Alasdair Scott ,  Philippe Marti

发明人： Steven Perry ,  Gregor Nixon ,  Alasdair Scott ,  Philippe Marti

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method for designing a system on a PLD is disclosed according to a first embodiment of the present invention. A logic design is optimized. Logic circuits from the logic design are mapped to resources on the PLD. At least some of the resources are fitted onto locations on the PLD by utilizing a user-specified procedure.

摘要翻译： 根据本发明的第一实施例公开了一种在PLD上设计系统的方法。 优化了逻辑设计。 来自逻辑设计的逻辑电路映射到PLD上的资源。 至少一些资源通过使用用户指定的过程被安装到PLD上的位置上。

公开(公告)号：US08001509B2

公开(公告)日：2011-08-16

申请号：US11858060

申请日：2007-09-19

申请人： Steven Perry ,  Gregor Nixon ,  Larry Kong ,  Alasdair Scott ,  Andrew Hall ,  Lingli Wang ,  Chris Dettmar ,  Jonathan Park ,  Richard Price

发明人： Steven Perry ,  Gregor Nixon ,  Larry Kong ,  Alasdair Scott ,  Andrew Hall ,  Lingli Wang ,  Chris Dettmar ,  Jonathan Park ,  Richard Price

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5054

摘要： A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

摘要翻译： 可以在可比较或兼容的用户可编程逻辑器件（“UPLD”）上设计用于掩模可编程逻辑器件（“MPLD”）的用户逻辑设计并迁移到MPLD，或者可以直接设计在MPLD上。 如果设计是在UPLD上设计的，则会考虑目标MPLD的约束，即设备之间的差异，以便迁移将成功。 如果设计直接在MPLD上设计，则如果用户指示设计将迁移到UPLD进行测试，则会考虑可比较的兼容UPLD的约束。 这意味着当逻辑设计旨在在UPLD和MPLD之间进行迁移时，只能使用特征交集。 为了便于迁移，可以创建成对的设备之间的固定映射。

公开(公告)号：US20080005716A1

公开(公告)日：2008-01-03

申请号：US11858060

申请日：2007-09-19

申请人： Steven Perry ,  Gregor Nixon ,  Larry Kong ,  Alasdair Scott ,  Andrew Hall ,  Lingli Wang ,  Chris Dettmar ,  Jonathan Park ,  Richard Price

发明人： Steven Perry ,  Gregor Nixon ,  Larry Kong ,  Alasdair Scott ,  Andrew Hall ,  Lingli Wang ,  Chris Dettmar ,  Jonathan Park ,  Richard Price

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5054

摘要： A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

摘要翻译： 可以在可比较或兼容的用户可编程逻辑器件（“UPLD”）上设计用于掩模可编程逻辑器件（“MPLD”）的用户逻辑设计并迁移到MPLD，或者可以直接设计在MPLD上。 如果设计是在UPLD上设计的，则会考虑目标MPLD的约束，即设备之间的差异，以便迁移将成功。 如果设计直接在MPLD上设计，则如果用户指示设计将迁移到UPLD进行测试，则会考虑可比较的兼容UPLD的约束。 这意味着当逻辑设计旨在在UPLD和MPLD之间进行迁移时，只能使用特征交集。 为了便于迁移，可以创建成对的设备之间的固定映射。

公开(公告)号：US07290237B2

公开(公告)日：2007-10-30

申请号：US10875256

申请日：2004-06-23

申请人： Steven Perry ,  Gregor Nixon ,  Larry Kong ,  Alasdair Scott ,  Andrew Hall ,  Lingli Wang ,  Chris Dettmar ,  Jonathan Park ,  Richard Price

发明人： Steven Perry ,  Gregor Nixon ,  Larry Kong ,  Alasdair Scott ,  Andrew Hall ,  Lingli Wang ,  Chris Dettmar ,  Jonathan Park ,  Richard Price

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5054

摘要： A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

摘要翻译： 可以在可比较或兼容的用户可编程逻辑器件（“UPLD”）上设计用于掩模可编程逻辑器件（“MPLD”）的用户逻辑设计并迁移到MPLD，或者可以直接设计在MPLD上。 如果设计是在UPLD上设计的，则会考虑目标MPLD的约束，即设备之间的差异，以便迁移将成功。 如果设计直接在MPLD上设计，则如果用户指示设计将迁移到UPLD进行测试，则会考虑可比较的兼容UPLD的约束。 这意味着当逻辑设计旨在在UPLD和MPLD之间进行迁移时，只能使用特征交集。 为了便于迁移，可以创建成对的设备之间的固定映射。

公开(公告)号：US07206967B1

公开(公告)日：2007-04-17

申请号：US10774731

申请日：2004-02-09

申请人： Philippe Marti ,  Mark Jervis ,  Gregor Nixon

发明人： Philippe Marti ,  Mark Jervis ,  Gregor Nixon

IPC分类号： G06F11/00

CPC分类号： G01R31/318364

摘要： While debugging, a user chooses an incremental recompile. Internal signals of interest and output pins are selected, and a number of additional registers are chosen to insert in the path of each internal signal. A clock is selected for the registers. An incremental recompile of the compiled design compiles a routing from each internal signal to an output pin via the added registers. The database building and logic synthesis stages are skipped. The post-fitting logical netlist and routing netlist are retrieved. The new registers are created and the internal signal is connected to the output pin atom in the logical netlist. The fitter places and routes the connections to create a new routing netlist and then the new routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The original routing netlist is undisturbed. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.

摘要翻译： 在调试时，用户选择增量重新编译。 选择感兴趣的内部信号和输出引脚，并且选择多个附加寄存器来插入每个内部信号的路径。 为寄存器选择一个时钟。 编译设计的增量重新编译通过添加的寄存器编译从每个内部信号到输出引脚的路由。 数据库构建和逻辑综合阶段被跳过。 检索后拟合逻辑网表和路由网表。 创建新的寄存器，并将内部信号连接到逻辑网表中的输出引脚原子。 装配者放置和路由连接以创建新的路由网表，然后将新的路由网表以适于编程PLD的形式输出到编程输出文件（POF）中。 原始路由网表不受干扰。 用户查看所选输出引脚上的内部信号。 为了调试PLD，用户可以多次迭代此过程。 调试分配可能会被删除。

公开(公告)号：US07234125B1

公开(公告)日：2007-06-19

申请号：US10874996

申请日：2004-06-23

申请人： Alasdair Scott ,  Gregor Nixon

发明人： Alasdair Scott ,  Gregor Nixon

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Programming software for mask-programmable logic devices provides a timing estimation to the user for the user's logic design during the compilation stage, notwithstanding that the software is not aware of the ultimate placement and routing of the design, which will be performed by the mask-programmable logic device supplier. The software includes a timing model based on actual delay measurements for different user designs in similar devices.

摘要翻译： 掩模可编程逻辑器件的编程软件在编译阶段为用户提供了用户逻辑设计的定时估计，尽管软件不知道设计的最终布局和路由，将由掩模可编程逻辑器件执行， 可编程逻辑器件供应商。 该软件包括基于类似设备中不同用户设计的实际延迟测量的时序模型。

公开(公告)号：US07530046B1

公开(公告)日：2009-05-05

申请号：US11437285

申请日：2006-05-18

申请人： Gregor Nixon ,  Mark Jervis ,  Zhengjun Pan ,  Gihan De Silva ,  Steven Perry

发明人： Gregor Nixon ,  Mark Jervis ,  Zhengjun Pan ,  Gihan De Silva ,  Steven Perry

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5077

摘要： While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.

摘要翻译： 在调试时，用户选择增量重新编译。 选择感兴趣的内部信号，并选择保留输出引脚。 编译设计的增量重新编译包括从每个内部信号编译到输出引脚的路由。 与原始编译设计对应的技术映射网表和放置和路由信息在完整编译期间保存到数据库中。 在调试期间，增量编译器检索此信息以构建原始路由网表。 可能会跳过数据库构建，逻辑综合和技术映射阶段。 添加新的连接，安装到设备，然后最终路由网表以适合于编程PLD的形式输出到编程输出文件（POF）中。 用户查看所选输出引脚上的内部信号。 为了调试PLD，用户可以多次迭代此过程。 调试分配可能会被删除。

公开(公告)号：US07076751B1

公开(公告)日：2006-07-11

申请号：US10351017

申请日：2003-01-24

申请人： Gregor Nixon ,  Mark Jervis ,  Zhengjun Pan ,  Gihan De Silva ,  Steven Perry

发明人： Gregor Nixon ,  Mark Jervis ,  Zhengjun Pan ,  Gihan De Silva ,  Steven Perry

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5054 ,  G06F17/5077

摘要： While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.