公开(公告)号：US06827505B2

公开(公告)日：2004-12-07

申请号：US10320844

申请日：2002-12-16

申请人： Subhash L. Shinde ,  L. Wynn Herron ,  Mario J. Interrante ,  How T. Lin ,  Steven P. Ostrander ,  Sudipta K. Ray ,  William E. Sablinski ,  Hilton Toy

发明人： Subhash L. Shinde ,  L. Wynn Herron ,  Mario J. Interrante ,  How T. Lin ,  Steven P. Ostrander ,  Sudipta K. Ray ,  William E. Sablinski ,  Hilton Toy

IPC分类号： G02B636

CPC分类号： G02B6/4201 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

摘要： An optical-electronic package for an electronic device provides electrical connections to the electronic device and optical fiber connections to the electronic device. The package includes a high thermal conductivity base which has a pedestal to support and provide heat transfer connection to the electronic device. A seal band is formed on the base and a casing is bonded to the seal band. The casing has side feedthroughs for the electrical connections from the electronic device, and the casing has top feedthroughs or grooves for the optical fiber connections from the electronic device. A lid is hermetically sealed to the top of the casing. The lid has retractable means for forming a bend in the optical fibers to provide strain relief when the lid is placed on the casing. The retractable means for forming a bend in the optical fibers is retractable once the lid is sealed on the casing.

公开(公告)号：US06762119B2

公开(公告)日：2004-07-13

申请号：US09885791

申请日：2001-06-20

申请人： Sudipta K. Ray ,  Mitchell S. Cohen ,  Lester Wynn Herron ,  Mario J. Interrante ,  Thomas E. Lombardi ,  Subhash L. Shinde

发明人： Sudipta K. Ray ,  Mitchell S. Cohen ,  Lester Wynn Herron ,  Mario J. Interrante ,  Thomas E. Lombardi ,  Subhash L. Shinde

IPC分类号： H01L2144

CPC分类号： H01S5/02272 ,  G02B6/4238 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01S5/02236 ,  H01S5/02268 ,  H01L2924/00 ,  H01L2924/00014

摘要： A process and structure for forming an optical subassembly in an integrated circuit, comprising: defining electrically conducting lines and bonding pads in a metallization layer on a substrate; depositing a passivation layer over the metallization layer; etching the passivation layer to remove the passivation layer from each of the bonding pads and a portion of the metallization layer associated with each of the bonding pads; diffusing Cr from the lines proximate said bonding pads to prevent solder wetting down lines; bonding an optical device to one of the bonding pads; and attaching the substrate to a carrier utilizing solder bond attachment.

摘要翻译： 一种用于在集成电路中形成光学子组件的工艺和结构，包括：在衬底上的金属化层中限定导电线和焊盘; 在所述金属化层上沉积钝化层; 蚀刻钝化层以从每个接合焊盘和与每个焊盘相关联的金属化层的一部分去除钝化层; 从靠近所述接合焊盘的线扩散Cr，以防止焊料向下润湿; 将光学器件接合到所述接合焊盘之一; 以及使用焊料粘合附着将衬底附接到载体上。

公开(公告)号：US20090163019A1

公开(公告)日：2009-06-25

申请号：US12348143

申请日：2009-01-02

申请人： Kamalesh K. Srivastava ,  Subhash L. Shinde ,  Tien-Jen Cheng ,  Sarah H. Knickerbocker ,  Roger A. Quon ,  William E. Sablinski ,  Julie C. Biggs ,  David E. Eichstadt ,  Jonathan H. Griffith

发明人： Kamalesh K. Srivastava ,  Subhash L. Shinde ,  Tien-Jen Cheng ,  Sarah H. Knickerbocker ,  Roger A. Quon ,  William E. Sablinski ,  Julie C. Biggs ,  David E. Eichstadt ,  Jonathan H. Griffith

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.

摘要翻译： 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 阻挡层形成在种子层的暴露部分上，由第一直径的第一图案化开口限定的暴露部分和使用第二直径的第二图案化开口在阻挡层上形成焊料材料。 第二图案化开口被配置为使得第二直径大于第一直径。

公开(公告)号：US07473997B2

公开(公告)日：2009-01-06

申请号：US11162468

申请日：2005-09-12

申请人： Kamalesh K. Srivastava ,  Subhash L. Shinde ,  Tien-Jen Cheng ,  Sarah H. Knickerbocker ,  Roger A. Quon ,  William E. Sablinski ,  Julie C. Biggs ,  David E. Eichstadt ,  Jonathan H. Griffith

发明人： Kamalesh K. Srivastava ,  Subhash L. Shinde ,  Tien-Jen Cheng ,  Sarah H. Knickerbocker ,  Roger A. Quon ,  William E. Sablinski ,  Julie C. Biggs ,  David E. Eichstadt ,  Jonathan H. Griffith

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

摘要翻译： 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 在种子层的暴露部分上形成阻挡层，暴露部分由第一图案化开口限定。 半导体器件被退火以使来自阻挡层的原子扩散到其中的晶种层中，其中退火使种子层的扩散区域相对于种子层的未扩散区域具有改变的电阻率和电极电位 。

公开(公告)号：US06995084B2

公开(公告)日：2006-02-07

申请号：US10708649

申请日：2004-03-17

申请人： Kamalesh K. Srivastava ,  Subhash L. Shinde ,  Tien-Jen Cheng ,  Sarah H. Knickerbocker ,  Roger A. Quon ,  William E. Sablinski ,  Julie C. Biggs ,  David E. Eichstadt ,  Jonathan H. Griffith

发明人： Kamalesh K. Srivastava ,  Subhash L. Shinde ,  Tien-Jen Cheng ,  Sarah H. Knickerbocker ,  Roger A. Quon ,  William E. Sablinski ,  Julie C. Biggs ,  David E. Eichstadt ,  Jonathan H. Griffith

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

公开(公告)号：US07767575B2

公开(公告)日：2010-08-03

申请号：US12348143

申请日：2009-01-02

申请人： Kamalesh K. Srivastava ,  Subhash L. Shinde ,  Tien-Jen Cheng ,  Sarah H. Knickerbocker ,  Roger A. Quinn ,  William E. Sablinski ,  Julie C. Biggs ,  David E. Eichstadt ,  Jonathan H. Griffith

发明人： Kamalesh K. Srivastava ,  Subhash L. Shinde ,  Tien-Jen Cheng ,  Sarah H. Knickerbocker ,  Roger A. Quinn ,  William E. Sablinski ,  Julie C. Biggs ,  David E. Eichstadt ,  Jonathan H. Griffith

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.

摘要翻译： 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 阻挡层形成在种子层的暴露部分上，由第一直径的第一图案化开口限定的暴露部分和使用第二直径的第二图案化开口在阻挡层上形成焊料材料。 第二图案化开口被配置为使得第二直径大于第一直径。

公开(公告)号：US08913856B2

公开(公告)日：2014-12-16

申请号：US10880289

申请日：2004-06-29

申请人： Lawrence Jacobowitz ,  John U. Knickerbocker ,  Ronald P. Luijten ,  Subhash L. Shinde

发明人： Lawrence Jacobowitz ,  John U. Knickerbocker ,  Ronald P. Luijten ,  Subhash L. Shinde

IPC分类号： G02B6/12 ,  G02B6/32 ,  G02B6/43 ,  G02B6/42

CPC分类号： G02B6/43 ,  G02B6/4228 ,  G02B6/4249

摘要： A set of interlocking modules supports and connects a die containing lasers, a set of precision molded lenses and a set of beam switching elements. Another embodiment of the invention is a structure for mounting a logic chip and an optical chip on a chip carrier, with the optical chip being mounted on the side of the carrier facing the system board on which the carrier is mounted, so that radiation travels in a straight path from optical sources on the optical chip into optical transmission guides on the board.

摘要翻译： 一组互锁模块支持并连接包含激光的模具，一组精密模制透镜和一组光束开关元件。 本发明的另一个实施例是用于将芯片和光学芯片安装在芯片载体上的结构，其中光学芯片被安装在载体侧面的载体侧面上，使得辐射在 从光学芯片上的光源到板上的光传输引导件的直线路径。

公开(公告)号：US08907439B1

公开(公告)日：2014-12-09

申请号：US13163909

申请日：2011-06-20

申请人： Randolph R. Kay ,  David V. Campbell ,  Subhash L. Shinde ,  Jeffrey L. Rienstra ,  Darwin K. Serkland ,  Michael L. Holmes ,  Seethambal S. Mani ,  Joy M. Barker ,  Dahwey Chu ,  Thomas Gurrieri

发明人： Randolph R. Kay ,  David V. Campbell ,  Subhash L. Shinde ,  Jeffrey L. Rienstra ,  Darwin K. Serkland ,  Michael L. Holmes ,  Seethambal S. Mani ,  Joy M. Barker ,  Dahwey Chu ,  Thomas Gurrieri

IPC分类号： H01L31/12

CPC分类号： H01L27/14634

摘要： A modular, scalable focal plane array is provided as an array of integrated circuit dice, wherein each die includes a given amount of modular pixel array circuitry. The array of dice effectively multiplies the amount of modular pixel array circuitry to produce a larger pixel array without increasing die size. Desired pixel pitch across the enlarged pixel array is preserved by forming die stacks with each pixel array circuitry die stacked on a separate die that contains the corresponding signal processing circuitry. Techniques for die stack interconnections and die stack placement are implemented to ensure that the desired pixel pitch is preserved across the enlarged pixel array.

摘要翻译： 提供了一种模块化的，可缩放的焦平面阵列作为集成电路芯片的阵列，其中每个管芯包括给定量的模块化像素阵列电路。 骰子阵列有效地将模块化像素阵列电路的数量乘以产生更大的像素阵列而不增加管芯尺寸。 通过将每个像素阵列电路管芯堆叠在包含对应的信号处理电路的单独的管芯上形成管芯堆叠来保留扩大的像素阵列上期望的像素间距。 实现用于管芯堆叠互连和管芯堆叠放置的技术以确保跨越扩大的像素阵列保留期望的像素间距。

公开(公告)号：US5552232A

公开(公告)日：1996-09-03

申请号：US361351

申请日：1994-12-21

申请人： Jon A. Casey ,  Carla N. Cordero ,  Benjamin V. Fasano ,  David B. Goland ,  Robert Hannon ,  Jonathan H. Harris ,  Lester W. Herron ,  Gregory M. Johnson ,  Niranjan M. Patel ,  Andrew M. Reitter ,  Subhash L. Shinde ,  Rao V. Vallabhaneni ,  Robert A. Youngman

发明人： Jon A. Casey ,  Carla N. Cordero ,  Benjamin V. Fasano ,  David B. Goland ,  Robert Hannon ,  Jonathan H. Harris ,  Lester W. Herron ,  Gregory M. Johnson ,  Niranjan M. Patel ,  Andrew M. Reitter ,  Subhash L. Shinde ,  Rao V. Vallabhaneni ,  Robert A. Youngman

IPC分类号： B32B18/00 ,  B22F7/02 ,  C04B35/581 ,  C04B37/02 ,  C04B41/51 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  C22C29/16 ,  H01L21/48 ,  H01L23/373 ,  H05K1/03 ,  H05K3/24 ,  H05K3/40 ,  H05K3/46 ,  B22F3/00

CPC分类号： C04B41/009 ,  B22F7/02 ,  C04B41/5133 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  C22C29/16 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3731 ,  H05K3/4061 ,  B22F2998/00 ,  C04B2111/00405 ,  C04B2111/00844 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/035 ,  H05K2201/09981 ,  H05K3/248 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T428/12021 ,  Y10T428/12028 ,  Y10T428/12056 ,  Y10T428/31678

摘要： Disclosed is an aluminum nitride body having graded metallurgy and a method for making such a body. The aluminum nitride body has at least one via and includes a first layer in direct contact with the aluminum nitride body and a second layer in direct contact with, and that completely encapsulates, the first layer. The first layer includes 30 to 60 volume percent aluminum nitride and 40 to 70 volume percent tungsten and/or molybdenum while the second layer includes 90 to 100 volume percent of tungsten and/or molybdenum and 0 to 10 volume percent of aluminum nitride.

公开(公告)号：US5520878A

公开(公告)日：1996-05-28

申请号：US438315

申请日：1995-05-10

申请人： Peter R. Duncombe ,  Subhash L. Shinde ,  Takeshi Takamori

发明人： Peter R. Duncombe ,  Subhash L. Shinde ,  Takeshi Takamori

IPC分类号： C04B35/581 ,  C04B35/622 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15 ,  B22F7/00

CPC分类号： H01L21/4807 ,  C04B35/581 ,  C04B35/622 ,  H01L23/15 ,  H01L2924/0002 ,  Y10T428/24917 ,  Y10T428/24926

摘要： An unsintered aluminum nitride body including:(a) 1 to 5 weight percent of a vitreous solid of boria, alumina, and calcia in the proportions of (1) boria between 3 and 25 weight percent, (2) alumina between 10 and 50 weight percent, and (3) calcia between 40 and 80 weight percent; and(b) aluminum nitride powder as the balance of the aluminum nitride body.The invention further relates to a method of forming the unsintered aluminum nitride body and then sintering it at a temperature between 1550 and 1650 degrees Centrigrade so as to form a dense, thermally conductive aluminum nitride body.

摘要翻译： 一种未烧结的氮化铝体，包括：（a）1至5重量％的氧化硼，氧化铝和氧化钙的玻璃状固体，其比例为（1）硼3重量％和25重量％，（2）10-50重量％的氧化铝 百分比，（3）钙化在40％和80％之间; 和（b）作为氮化铝体的平衡的氮化铝粉末。 本发明还涉及形成未烧结氮化铝体的方法，然后在1550和1650摄氏度之间的温度下烧结，以形成致密的导热氮化铝体。