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公开(公告)号：US20140291615A1
公开(公告)日：2014-10-02
申请号：US14302371
申请日：2014-06-11
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L29/15
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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公开(公告)号：US08530884B2
公开(公告)日：2013-09-10
申请号：US13160886
申请日：2011-06-15
申请人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
发明人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L29/06 , H01L31/072
CPC分类号： H01L29/1033 , H01L29/0673 , H01L29/201 , H01L29/205 , H01L29/41725 , H01L29/66431 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66787 , H01L29/775 , H01L29/78 , H01L29/785
摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
摘要翻译： 描述形成应变诱导半导体区域的方法。 在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。 在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及 其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。
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3.发明授权Mechanism for forming a remote delta doping layer of a quantum well structure 有权用于形成量子阱结构的远程δ掺杂层的机理公开(公告)号：US08264004B2
公开(公告)日：2012-09-11
申请号：US12715034
申请日：2010-03-01
IPC分类号： H01L29/778
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。
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公开(公告)号：US20120199813A1
公开(公告)日：2012-08-09
申请号：US13450359
申请日：2012-04-18
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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5.发明授权Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 有权隧道场效应晶体管使用成角度的植入物形成不对称的源极/漏极区域公开(公告)号：US07888221B2
公开(公告)日：2011-02-15
申请号：US12229459
申请日：2008-08-22
申请人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
发明人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/7391
摘要： The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
摘要翻译： 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（TFET），其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区。
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6.发明授权Mechanism for forming a remote delta doping layer of a quantum well structure 有权用于形成量子阱结构的远程δ掺杂层的机理公开(公告)号：US07713803B2
公开(公告)日：2010-05-11
申请号：US11731266
申请日：2007-03-29
IPC分类号： H01L21/336
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。
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公开(公告)号：US20140103396A1
公开(公告)日：2014-04-17
申请号：US14133457
申请日：2013-12-18
申请人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
发明人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
CPC分类号： H01L29/1033 , H01L29/0673 , H01L29/201 , H01L29/205 , H01L29/41725 , H01L29/66431 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66787 , H01L29/775 , H01L29/78 , H01L29/785
摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
摘要翻译： 描述形成应变诱导半导体区域的方法。 在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。 在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及 其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。
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8.发明授权公开(公告)号：US08120065B2
公开(公告)日：2012-02-21
申请号：US12541763
申请日：2009-08-14
IPC分类号： H01L21/02
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/517 , H01L29/66628 , H01L29/7848 , Y10S438/933 , Y10S438/938
摘要： Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
摘要翻译： 描述了增强模式晶体管，其中在源极和漏极区域中使用III-N族化合物以在通道上施加拉伸应变。 源极和漏极区域可以被凸起或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。
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9.发明申请CMOS DEVICES WITH A SINGLE WORK FUNCTION GATE ELECTRODE AND METHOD OF FABRICATION 有权具有单个工作功能门电极的CMOS器件及其制造方法公开(公告)号：US20110180851A1
公开(公告)日：2011-07-28
申请号：US13038190
申请日：2011-03-01
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/772
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。
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10.发明申请Mechanism for Forming a Remote Delta Doping Layer of a Quantum Well Structure 有权形成量子阱结构的远程三角形掺杂层的机理公开(公告)号：US20100219396A1
公开(公告)日：2010-09-02
申请号：US12715034
申请日：2010-03-01
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。
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