公开(公告)号：US08658476B1

公开(公告)日：2014-02-25

申请号：US13452657

申请日：2012-04-20

申请人： Xin Sun ,  Sung Hyun Jo ,  Tanmay Kumar

发明人： Xin Sun ,  Sung Hyun Jo ,  Tanmay Kumar

IPC分类号： H01L27/112 ,  H01L21/82 ,  H01L21/20 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L45/145 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1675

摘要： A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.

摘要翻译： 一种形成非易失性存储器件的方法。 该方法包括提供具有表面区域并形成覆盖在基板的表面区域上的第一介电材料的基板。 形成第一电极结构，覆盖第一电介质材料，并且形成覆盖第一电极结构的p +多晶硅锗材料。 在大约430摄氏度至大约475摄氏度的沉积温度下，使用多晶硅锗材料作为种子层，形成覆盖第一电极结构的p +多晶硅材料，而无需进一步退火。 该方法形成覆盖多晶硅材料的电阻开关材料，以及包括覆盖电阻开关材料的活性金属材料的第二电极结构。

公开(公告)号：US08971088B1

公开(公告)日：2015-03-03

申请号：US13426869

申请日：2012-03-22

申请人： Sung Hyun Jo ,  Tanmay Kumar

发明人： Sung Hyun Jo ,  Tanmay Kumar

IPC分类号： G11C11/00

CPC分类号： G11C11/5628 ,  G11C11/1675 ,  G11C11/2275 ,  G11C11/56 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2211/562 ,  G11C2211/5648 ,  G11C2213/15

摘要： A method for programming a non-volatile memory device includes providing an as-fabricated state-change device having an aluminum doped zinc oxide material first electrode, a p++ polysilicon material second electrode, and a zinc oxide (ZnO) material state-change material there between. A first amplitude bias voltage is applied to the first electrode of the as-fabricated state-change device causing the ZnO material to change form an as-fabricated state to a first state. A second amplitude bias voltage having an opposite polarity having an amplitude similar to the first amplitude is applied to cause the ZnO to change from the first state to a second state substantially similar as the as-fabricated state. A third amplitude bias voltage having a same polarity to the first bias voltage and having an amplitude dissimilar to the first bias voltage is applied to cause the ZnO to change from the second state to a third state.

摘要翻译： 用于编程非易失性存储器件的方法包括提供一种具有铝掺杂氧化锌材料第一电极，p ++多晶硅材料第二电极和氧化锌（ZnO）材料状态变化材料的制造状态改变器件 之间。 第一幅度偏置电压被施加到制造状态改变器件的第一电极，使得ZnO材料从制造状态改变到第一状态。 施加具有与第一幅度相似的振幅相反极性的第二幅度偏置电压，以使ZnO从第一状态转变为与制造状态基本相似的第二状态。 施加与第一偏置电压具有相同极性且具有与第一偏置电压不同的幅度的第三幅度偏置电压，以使ZnO从第二状态变为第三状态。

公开(公告)号：US08946669B1

公开(公告)日：2015-02-03

申请号：US13586815

申请日：2012-08-15

申请人： Sung Hyun Jo ,  Kuk-Hwan Kim ,  Tanmay Kumar

发明人： Sung Hyun Jo ,  Kuk-Hwan Kim ,  Tanmay Kumar

IPC分类号： H01L29/02

CPC分类号： H01L27/2463 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/148 ,  H01L45/1633 ,  H01L45/1675

摘要： A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.

摘要翻译： 一种用于形成电阻式存储器件的方法包括提供包括第一金属材料的衬底，在第一金属材料的顶部上形成导电含硅层，其中导电含硅层包括上部区域和下部区域，以及 其中所述下部区域与所述第一金属材料相邻，从所述导电含硅层的上部区域形成非晶层，并且在所述非晶层的上方设置活性金属材料。

公开(公告)号：US09058865B1

公开(公告)日：2015-06-16

申请号：US13525096

申请日：2012-06-15

申请人： Sung Hyun Jo ,  Tanmay Kumar

发明人： Sung Hyun Jo ,  Tanmay Kumar

IPC分类号： G11C13/00

CPC分类号： G11C13/00 ,  G11C11/56 ,  G11C11/5614 ,  G11C13/0002 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/33

摘要： A method of programming a non-volatile memory device includes providing a resistive switching device, the resistive switching device being in a first state and characterized by at least a first resistance, applying a first voltage to the resistive switching device in the first state to cause the resistive switching device to change to a second state wherein the second state is characterized by at least a second resistance, wherein the second resistance is greater than the first resistance, and applying a second voltage to the resistive switching device in the second state to cause the resistive switching device to change to a third state, wherein the third state is characterized by at least a third resistance, wherein the second voltage has a magnitude higher than a magnitude of the second voltage, and wherein the third resistance is greater than the second resistance.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括：提供电阻式开关器件，所述电阻开关器件处于第一状态，其特征在于至少第一电阻，在所述第一状态下向所述电阻开关器件施加第一电压以引起 所述电阻式开关装置改变为第二状态，其中所述第二状态的特征在于至少第二电阻，其中所述第二电阻大于所述第一电阻，并且在所述第二状态下向所述电阻式开关装置施加第二电压以引起 所述电阻性开关器件改变为第三状态，其中所述第三状态的特征在于至少第三电阻，其中所述第二电压具有高于所述第二电压的幅度的幅度，并且其中所述第三电阻大于所述第二电阻 抵抗性。

公开(公告)号：US08569172B1

公开(公告)日：2013-10-29

申请号：US13585759

申请日：2012-08-14

申请人： Sung Hyun Jo ,  Kuk-Hwan Kim ,  Tanmay Kumar

发明人： Sung Hyun Jo ,  Kuk-Hwan Kim ,  Tanmay Kumar

IPC分类号： H01L21/44 ,  H01L21/00

CPC分类号： H01L45/146 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1675

摘要： A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.

摘要翻译： 一种用于形成非易失性存储器件的方法包括设置包括掺杂的含硅材料与第一导电材料电接触的结层，在至少一部分所述第一导电材料上形成包含未掺杂的非晶硅承载材料的开关层 将包含非贵金属材料的层设置在所述开关层的至少一部分上，在所述层的至少一部分上设置包含贵金属材料的活性金属层，以及在所述第一导电材料的至少一部分上形成第二导电材料 与活性金属层接触。

公开(公告)号：US08754671B2

公开(公告)日：2014-06-17

申请号：US13194479

申请日：2011-07-29

申请人： Hagop Nazarian ,  Sang Thanh Nguyen ,  Tanmay Kumar

发明人： Hagop Nazarian ,  Sang Thanh Nguyen ,  Tanmay Kumar

IPC分类号： H03K19/0944 ,  H03K19/177 ,  G11C11/00

CPC分类号： H03K19/17776 ,  G11C13/0021 ,  H01L27/101 ,  H03K19/0013 ,  H03K19/00315 ,  H03K19/0944 ,  H03K19/1776

摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

公开(公告)号：US08450835B2

公开(公告)日：2013-05-28

申请号：US12149217

申请日：2008-04-29

申请人： Xiying Chen ,  Mark H. Clark ,  S. Brad Herner ,  Tanmay Kumar

发明人： Xiying Chen ,  Mark H. Clark ,  S. Brad Herner ,  Tanmay Kumar

IPC分类号： H01L29/06

CPC分类号： H01L29/868 ,  H01L29/1606 ,  H01L29/8615

摘要： One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

公开(公告)号：US08072791B2

公开(公告)日：2011-12-06

申请号：US11819041

申请日：2007-06-25

申请人： S. Brad Herner ,  Mark H. Clark ,  Tanmay Kumar

发明人： S. Brad Herner ,  Mark H. Clark ,  Tanmay Kumar

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： G11C11/36 ,  H01L27/101 ,  H01L27/1021

摘要： A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell.

摘要翻译： 制造非易失性存储器件的方法包括：形成第一电极，形成至少一个包括硅，锗或硅 - 锗二极管的非易失性存储单元，用氮或碳中的至少一种掺杂二极管，并形成第二电极 所述至少一个非易失性存储单元。

公开(公告)号：US20110021019A1

公开(公告)日：2011-01-27

申请号：US12897696

申请日：2010-10-04

申请人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

发明人： Michael W. Konevecki ,  Usha Raghuram ,  Maitreyee Mahajani ,  Sucheta Nallamothu ,  Andrew J. Walker ,  Tanmay Kumar

IPC分类号： H01L21/768

CPC分类号： H01L27/12 ,  H01L21/28282 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

摘要翻译： 本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。 多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。 根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。 类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

公开(公告)号：US07875871B2

公开(公告)日：2011-01-25

申请号：US11395419

申请日：2006-03-31

申请人： Tanmay Kumar ,  S. Brad Herner

发明人： Tanmay Kumar ,  S. Brad Herner

IPC分类号： H04L29/02 ,  H04L47/00

CPC分类号： H01L29/868 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/165 ,  H01L29/22 ,  H01L29/267 ,  H01L29/417 ,  H01L29/737 ,  H01L29/8615 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

摘要： In the present invention a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.

摘要翻译： 在本发明中，作为宽带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。 该p-n异质结可以用于各种装置中。 在优选实施例中，垂直取向的p-i-n异质结二极管的一个端子是金属氧化物或氮化物层，而二极管的其余部分由硅或硅 - 锗电阻器形成; 例如二极管可以包括重掺杂的n型硅区，本征硅区和用作p型端的氧化镍层。 这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单片三维存储器阵列中。