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    Nonvolatile memory devices and methods of manufacturing the same
    1.
    发明授权
    Nonvolatile memory devices and methods of manufacturing the same 失效
    非易失存储器件及其制造方法

    公开(公告)号：US08264026B2

    公开(公告)日：2012-09-11

    申请号：US12694655

    申请日：2010-01-27

    申请人： Sung-Hae Lee ,  Byong-Sun Ju ,  Suk-Jin Chung ,  Young-Sun Kim

    发明人： Sung-Hae Lee ,  Byong-Sun Ju ,  Suk-Jin Chung ,  Young-Sun Kim

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

    摘要： Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.

    摘要翻译： 提供了非易失性存储器件及其制造方法。 非易失性存储器件包括衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的栅极间电介质层结构以及栅极间电介质层结构上的控制栅极。 栅极间电介质层结构包括第一氧化硅层，第一氧化硅层上的高电介质层和与第一氧化硅层相对的高电介质层上的第二氧化硅层。高电介质层可以包括第一氧化硅层 和第二高介电层彼此层叠，并且第一高介电层可以具有比第二高介电层更低的电子陷阱位置密度，并且可以具有比第二高介电层更大的能带隙或导带偏移 。

    NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20100187595A1

    公开(公告)日：2010-07-29

    申请号：US12694655

    申请日：2010-01-27

    申请人： Sung-Hae Lee ,  Byong-Sun Ju ,  Suk-Jin Chung ,  Young-Sun Kim

    发明人： Sung-Hae Lee ,  Byong-Sun Ju ,  Suk-Jin Chung ,  Young-Sun Kim

    IPC分类号： H01L29/788 ,  H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

    摘要： Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.

    摘要翻译： 提供了非易失性存储器件及其制造方法。 非易失性存储器件包括衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的栅极间电介质层结构以及栅极间电介质层结构上的控制栅极。 栅极间电介质层结构包括第一氧化硅层，第一氧化硅层上的高电介质层和与第一氧化硅层相对的高电介质层上的第二氧化硅层。高电介质层可以包括第一氧化硅层 和第二高介电层彼此层叠，并且第一高介电层可以具有比第二高介电层更低的电子陷阱位置密度，并且可以具有比第二高介电层更大的能带隙或导带偏移 。

    Methods of forming integrated circuit devices including a capacitor
    7.
    发明授权
    Methods of forming integrated circuit devices including a capacitor 有权
    形成包括电容器的集成电路器件的方法

    公开(公告)号：US08318560B2

    公开(公告)日：2012-11-27

    申请号：US11680148

    申请日：2007-02-28

    申请人： Wan-Don Kim ,  Cha-Young Yoo ,  Suk-Jin Chung ,  Jin-Yong Kim

    发明人： Wan-Don Kim ,  Cha-Young Yoo ,  Suk-Jin Chung ,  Jin-Yong Kim

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/65 ,  H01L28/55 ,  H01L28/91

    摘要： Methods of forming a capacitor of an integrated circuit device include forming a lower electrode of the capacitor on an integrated circuit substrate without exposing a contact plug to be coupled to the lower electrode. A supporting conductor is formed coupling the lower electrode to the contact plug after forming the lower electrode. A capacitor dielectric layer is formed on the lower electrode and an upper electrode of the capacitor is formed on the capacitor dielectric layer.

    摘要翻译： 形成集成电路器件的电容器的方法包括在集成电路衬底上形成电容器的下电极，而不会暴露要耦合到下电极的接触插头。 在形成下电极之后，形成将下电极耦合到接触插塞的支撑导体。 电容器电介质层形成在下电极上，电容器的上电极形成在电容器电介质层上。

    Methods of forming metal layers using oxygen gas as a reaction source and methods of fabricating capacitors using such metal layers
    8.
    发明授权
    Methods of forming metal layers using oxygen gas as a reaction source and methods of fabricating capacitors using such metal layers 有权
    使用氧气作为反应源形成金属层的方法和使用这种金属层制造电容器的方法

    公开(公告)号：US07842581B2

    公开(公告)日：2010-11-30

    申请号：US11616406

    申请日：2006-12-27

    申请人： Suk-Jin Chung ,  Jin-Yong Kim ,  Wan-Don Kim ,  Kwang-Hee Lee ,  Cha-Young Yoo

    发明人： Suk-Jin Chung ,  Jin-Yong Kim ,  Wan-Don Kim ,  Kwang-Hee Lee ,  Cha-Young Yoo

    IPC分类号： H01L21/20

    CPC分类号： H01L21/28562 ,  C23C16/06 ,  C23C16/45542 ,  H01L28/65

    摘要： When a metal layer formed by reaction of a metal source and an oxygen (O2) source is deposited, oxidization of a conductive layer disposed under or on the metal layer can be reduced and/or prevented by a method of forming the metal layer and a method of fabricating a capacitor using the same. Between forming the conductive layer and the metal layer, and between forming the metal layer and the conductive layer, a cycle of supplying a metal source, purging, supplying an oxygen source, purging, plasma processing of reduction gas and purging is repeated at least once. In this case, the metal layer is formed by repeating a cycle of supplying a metal source, purging, supplying an oxygen source and purging.

    摘要翻译： 当沉积由金属源和氧（O 2）源反应而形成的金属层时，可通过形成金属层的方法和/或通过形成金属层的方法来减少和/或防止设置在金属层下面或金属层上的导电层的氧化 制造使用该电容器的电容器的方法。 在形成导电层和金属层之间，并且在形成金属层和导电层之间，重复提供金属源，净化，供应氧源，净化，还原气体的等离子体处理和清洗的循环至少一次 。 在这种情况下，通过重复提供金属源，净化，供应氧源和清洗的循环来形成金属层。

    Method for forming dielectric layer of capacitor
    9.
    发明授权
    Method for forming dielectric layer of capacitor 失效
    电容器介质层形成方法

    公开(公告)号：US07416904B2

    公开(公告)日：2008-08-26

    申请号：US10293530

    申请日：2002-11-12

    申请人： Jae-Hyoung Choi ,  Cha-Young Yoo ,  Suk-Jin Chung ,  Wan-Don Kim

    发明人： Jae-Hyoung Choi ,  Cha-Young Yoo ,  Suk-Jin Chung ,  Wan-Don Kim

    IPC分类号： H01L21/00 ,  H01L21/8242 ,  H01L21/8222 ,  H01L21/20

    CPC分类号： H01L21/02183 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/55

    摘要： A fabrication method for forming a semiconductor device having a capacitor is provided. A capacitor dielectric layer is formed by depositing a first layer and a second layer. The second layer is a major portion of the capacitor dielectric layer. The first layer acts as a seed layer, while the second layer is expitaxially grown. The material of the second layer as deposited is partially crystal. Nuclear generation and crystal growth occur separately so that the crystalline characteristic of the capacitor dielectric layer and the capacitance characteristic of the capacitor are enhanced. Moreover, the capacitor dielectric layer is crystallized at a relatively low temperature or for a relatively short time, thereby reducing leakage current as well as reducing deformation in the lower electrode. Optionally, The material of the second layer as deposited is not partially crystal but amorphous.

    摘要翻译： 提供一种用于形成具有电容器的半导体器件的制造方法。 通过沉积第一层和第二层形成电容器电介质层。 第二层是电容器介电层的主要部分。 第一层用作种子层，而第二层被外延生长。 沉积的第二层的材料是部分晶体的。 核生成和晶体生长分开发生，使得电容器介电层的晶体特性和电容器的电容特性得到增强。 此外，电容器电介质层在相对较低的温度或相当短的时间内结晶，从而减少漏电流以及减小下电极的变形。 任选地，沉积的第二层的材料不是部分晶体而是无定形的。

    Integrated Circuit Devices Including a Capacitor and Methods of Forming the Same
    10.
    发明申请
    Integrated Circuit Devices Including a Capacitor and Methods of Forming the Same 有权
    包括电容器的集成电路器件及其形成方法

    公开(公告)号：US20070207587A1

    公开(公告)日：2007-09-06

    申请号：US11680148

    申请日：2007-02-28

    申请人： Wan-Don Kim ,  Cha-Young Yoo ,  Suk-Jin Chung ,  Jin-Yong Kim

    发明人： Wan-Don Kim ,  Cha-Young Yoo ,  Suk-Jin Chung ,  Jin-Yong Kim

    IPC分类号： H01L21/20

    CPC分类号： H01L28/65 ,  H01L28/55 ,  H01L28/91

    摘要： Methods of forming a capacitor of an integrated circuit device include forming a lower electrode of the capacitor on an integrated circuit substrate without exposing a contact plug to be coupled to the lower electrode. A supporting conductor is formed coupling the lower electrode to the contact plug after forming the lower electrode. A capacitor dielectric layer is formed on the lower electrode and an upper electrode of the capacitor is formed on the capacitor dielectric layer.

    摘要翻译： 形成集成电路器件的电容器的方法包括在集成电路衬底上形成电容器的下电极，而不会暴露要耦合到下电极的接触插头。 在形成下电极之后，形成将下电极耦合到接触插塞的支撑导体。 电容器电介质层形成在下电极上，电容器的上电极形成在电容器电介质层上。