公开(公告)号：US09275904B2

公开(公告)日：2016-03-01

申请号：US12614991

申请日：2009-11-09

申请人： Sung-Jin Whang ,  Moon-Sig Joo ,  Yong-Seok Eun ,  Kwon Hong ,  Bo-Min Seo ,  Kyoung-Eun Chang ,  Seung-Woo Shin

发明人： Sung-Jin Whang ,  Moon-Sig Joo ,  Yong-Seok Eun ,  Kwon Hong ,  Bo-Min Seo ,  Kyoung-Eun Chang ,  Seung-Woo Shin

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L21/823443 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32139 ,  H01L27/10873 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42376 ,  H01L29/4933

摘要： A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成栅极图案，形成覆盖每个栅极图案的顶部和侧壁的导电层，在导电层上形成用于硅化工艺的金属层，以及硅化导电层和栅极图案 使用金属层。

公开(公告)号：US20100283096A1

公开(公告)日：2010-11-11

申请号：US12640491

申请日：2009-12-17

申请人： Sung-Jin Whang ,  Moon-Sig Joo ,  Kwon Hong ,  Jung-Yeon Lim ,  Won-Kyu Kim ,  Bo-Min Seo ,  Kyoung-Eun Chang

发明人： Sung-Jin Whang ,  Moon-Sig Joo ,  Kwon Hong ,  Jung-Yeon Lim ,  Won-Kyu Kim ,  Bo-Min Seo ,  Kyoung-Eun Chang

IPC分类号： H01L29/792 ,  H01L23/48 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/321 ,  H01L21/7685 ,  H01L24/02 ,  H01L27/10873 ,  H01L29/413 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/12032 ,  H01L2924/00

摘要： A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.

摘要翻译： 一种半导体器件，包括导电层，形成在导电层上的扩散阻挡层，包括难熔金属化合物，并在表面处理之后获得，以及形成在扩散阻挡层上的金属硅化物层。 通过表面处理增加扩散阻挡层的表面能，可以改善扩散阻挡层和金属硅化物层之间的粘合性。 因此，尽管金属硅化物层在高温工艺中熔合，但是可以防止在扩散阻挡层和金属硅化物层之间的界面处产生空隙。 此外，通过表面处理增加导电层的表面能，可以增加导电层与扩散阻挡层之间的粘合性。

公开(公告)号：US08847300B2

公开(公告)日：2014-09-30

申请号：US12640491

申请日：2009-12-17

申请人： Sung-Jin Whang ,  Moon-Sig Joo ,  Kwon Hong ,  Jung-Yeon Lim ,  Won-Kyu Kim ,  Bo-Min Seo ,  Kyoung-Eun Chang

发明人： Sung-Jin Whang ,  Moon-Sig Joo ,  Kwon Hong ,  Jung-Yeon Lim ,  Won-Kyu Kim ,  Bo-Min Seo ,  Kyoung-Eun Chang

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L27/108 ,  H01L29/423 ,  H01L21/28 ,  H01L23/00 ,  H01L21/321 ,  H01L29/41

CPC分类号： H01L21/28518 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/321 ,  H01L21/7685 ,  H01L24/02 ,  H01L27/10873 ,  H01L29/413 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/12032 ,  H01L2924/00

摘要： A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.

摘要翻译： 一种半导体器件，包括导电层，形成在导电层上的扩散阻挡层，包括难熔金属化合物，并在表面处理之后获得，以及形成在扩散阻挡层上的金属硅化物层。 通过表面处理增加扩散阻挡层的表面能，可以改善扩散阻挡层和金属硅化物层之间的粘合性。 因此，尽管金属硅化物层在高温工艺中熔合，但是可以防止在扩散阻挡层和金属硅化物层之间的界面处产生空隙。 此外，通过表面处理增加导电层的表面能，可以增加导电层与扩散阻挡层之间的粘合性。

公开(公告)号：US09019767B2

公开(公告)日：2015-04-28

申请号：US13398397

申请日：2012-02-16

申请人： Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

发明人： Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C16/14

CPC分类号： G11C16/14 ,  G11C16/0408 ,  H01L27/11556 ,  H01L27/11582

摘要： A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

摘要翻译： 非易失性存储器件包括从衬底垂直延伸的沟道，沿着沟道堆叠的多个存储单元; 连接到所述沟道的第一端部的源极区域和与所述沟道的第二端部连接的位线，其中与所述源极区域相邻的所述沟道的所述第一端部形成为未掺杂的半导体层或半导体 层掺杂有P型杂质。

公开(公告)号：US08928063B2

公开(公告)日：2015-01-06

申请号：US13618182

申请日：2012-09-14

申请人： Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

发明人： Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

IPC分类号： H01L29/792 ,  H01L21/20

CPC分类号： H01L21/28282 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/792

摘要： A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.

摘要翻译： 非易失性存储器件包括从衬底垂直延伸的沟道层，沿着沟道层交替层叠的多个层间电介质层和多个栅极电极，以及插入在沟道层和每个沟道层之间的气隙 的多个栅电极。 非易失性存储器件可以通过用插入位于栅电极和具有气隙的电荷存储层之间的电荷阻挡层来抑制电子的反向隧道而提高擦除操作特性，以及制造非易失性存储器件的方法。

公开(公告)号：US08711630B2

公开(公告)日：2014-04-29

申请号：US13334423

申请日：2011-12-22

申请人： Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

发明人： Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  H01L27/11556

摘要： A programming method of a non-volatile memory device that includes a string of memory cells with a plurality of floating gates and a plurality of control gates disposed alternately, wherein each of the memory cells includes one floating gate and two control gates disposed adjacent to the floating gate and two neighboring memory cells share one control gate. The programming method includes applying a first program voltage to a first control gate of a selected memory cell and a second program voltage that is higher than the first program voltage to a second control gate of the selected memory cell, and applying a first pass voltage to a third control gate disposed adjacent to the first control gate and a second pass voltage that is lower than the first pass voltage to a fourth control gate disposed adjacent to the second control gate.

摘要翻译： 一种非易失性存储器件的编程方法，包括具有多个浮动栅极和多个控制栅极交替布置的存储器单元串，其中每个存储器单元包括一个浮置栅极和两个控制栅极， 浮动门和两个相邻的存储单元共享一个控制门。 编程方法包括将第一编程电压施加到所选择的存储单元的第一控制栅极，以及将高于第一编程电压的第二编程电压施加到所选存储单元的第二控制栅极，并将第一通过电压施加到 与第一控制栅极相邻设置的第三控制栅极和与第二控制栅极相邻设置的第四控制栅极低于第一通过电压的第二通过电压。

公开(公告)号：US08928059B2

公开(公告)日：2015-01-06

申请号：US13605213

申请日：2012-09-06

申请人： Sung-Jin Whang ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Min-Soo Kim

发明人： Sung-Jin Whang ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Min-Soo Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11556 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7889

摘要： A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.

摘要翻译： 非易失性存储器件包括：衬底; 从所述基板的表面在垂直于所述表面的方向上突出的沟道层; 围绕所述沟道层的隧道介电层; 多个层间电介质层和沿沟道层交替形成的多个控制栅电极; 插入在隧道介电层和多个控制栅电极之间的浮置栅电极，浮置栅电极包括金属 - 半导体化合物; 以及插入在所述多个控制栅极电极和所述多个浮栅电极中的每一个之间的电荷阻挡层。

公开(公告)号：US08860119B2

公开(公告)日：2014-10-14

申请号：US13604073

申请日：2012-09-05

申请人： Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

发明人： Min-Soo Kim ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Sung-Jin Whang

IPC分类号： H01L29/78 ,  H01L21/283

CPC分类号： H01L27/11582

摘要： A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.

摘要翻译： 非易失性存储器件包括：衬底，其包括表面，形成在所述衬底的表面上的从所述表面垂直突出的沟道层，以及沿所述沟道层交替堆叠的多个层间电介质层和多个栅极电极层， 其中所述多个栅极电极层从所述多个层间电介质层突出。

公开(公告)号：US20130264629A1

公开(公告)日：2013-10-10

申请号：US13605213

申请日：2012-09-06

申请人： Sung-Jin Whang ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Min-Soo Kim

发明人： Sung-Jin Whang ,  Dong-Sun Sheen ,  Seung-Ho Pyi ,  Min-Soo Kim

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11556 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7889

摘要： A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.

公开(公告)号：US20120170371A1

公开(公告)日：2012-07-05

申请号：US13334423

申请日：2011-12-22

申请人： Seiichi ARITOME ,  Hyun-Seung Yoo ,  Sung-Jin Whang

发明人： Seiichi ARITOME ,  Hyun-Seung Yoo ,  Sung-Jin Whang

IPC分类号： G11C16/10

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  H01L27/11556

摘要： A programming method of a non-volatile memory device that includes a string of memory cells with a plurality of floating gates and a plurality of control gates disposed alternately, wherein each of the memory cells includes one floating gate and two control gates disposed adjacent to the floating gate and two neighboring memory cells share one control gate. The programming method includes applying a first program voltage to a first control gate of a selected memory cell and a second program voltage that is higher than the first program voltage to a second control gate of the selected memory cell, and applying a first pass voltage to a third control gate disposed adjacent to the first control gate and a second pass voltage that is lower than the first pass voltage to a fourth control gate disposed adjacent to the second control gate.

摘要翻译： 一种非易失性存储器件的编程方法，包括具有多个浮动栅极和多个控制栅极交替布置的存储器单元串，其中每个存储器单元包括一个浮置栅极和两个控制栅极， 浮动门和两个相邻的存储单元共享一个控制门。 编程方法包括将第一编程电压施加到所选择的存储单元的第一控制栅极，以及将高于第一编程电压的第二编程电压施加到所选存储单元的第二控制栅极，并将第一通过电压施加到 与第一控制栅极相邻设置的第三控制栅极和与第二控制栅极相邻设置的第四控制栅极低于第一通过电压的第二通过电压。