公开(公告)号：US20080272355A1

公开(公告)日：2008-11-06

申请号：US12110206

申请日：2008-04-25

申请人： Sung-Lae Cho ,  Byoung-Jae Bae ,  Jin-Il Lee ,  Hye-Young Park ,  Young-Lim Park ,  Rak-Hwan Kim

发明人： Sung-Lae Cho ,  Byoung-Jae Bae ,  Jin-Il Lee ,  Hye-Young Park ,  Young-Lim Park ,  Rak-Hwan Kim

IPC分类号： H01L47/00 ,  H01L21/00

CPC分类号： H01L45/1683 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144

摘要： A memory device using a phase change material and a method for forming the same are disclosed. One embodiment of a memory device includes a first insulating layer provided on a substrate and defining an opening; a first conductor including a first portion and a second portion, the first portion provided on a bottom of the opening, the second portion being continuously provided along a sidewall of the opening; a variable resistor connected to the second portion of the first conductor and provided along the sidewall of the opening; and a second conductor provided on the variable resistor.

摘要翻译： 公开了使用相变材料的记忆装置及其形成方法。 存储器件的一个实施例包括设置在衬底上并限定开口的第一绝缘层; 包括第一部分和第二部分的第一导体，所述第一部分设置在所述开口的底部上，所述第二部分沿着所述开口的侧壁连续设置; 连接到第一导体的第二部分并沿着开口的侧壁设置的可变电阻器; 以及设置在可变电阻器上的第二导体。

公开(公告)号：US20120165759A1

公开(公告)日：2012-06-28

申请号：US13046191

申请日：2011-03-11

申请人： John A. Rogers ,  Rak-Hwan Kim ,  Dae-Hyeong Kim ,  David L. Kaplan ,  Fiorenzo G. Omenetto

发明人： John A. Rogers ,  Rak-Hwan Kim ,  Dae-Hyeong Kim ,  David L. Kaplan ,  Fiorenzo G. Omenetto

IPC分类号： A61M25/00 ,  G01J1/42 ,  H05K3/20 ,  G01F1/66 ,  A61L17/00 ,  A61N5/06

CPC分类号： H05K1/0283 ,  A61B5/0422 ,  A61B5/6806 ,  A61B5/6867 ,  A61B5/6883 ,  A61B2562/02 ,  A61B2562/0233 ,  A61B2562/0257 ,  A61B2562/0271 ,  A61B2562/066 ,  A61B2562/12 ,  A61B2562/164 ,  A61N1/05 ,  A61N1/18 ,  A61N1/36 ,  F21K9/00 ,  H01L23/3121 ,  H01L23/3192 ,  H01L27/1218 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/147 ,  H05K3/323 ,  H05K2201/09263 ,  H05K2201/10106 ,  H05K2203/1316 ,  Y10T29/49128 ,  H01L2924/00

摘要： Described herein are flexible and stretchable LED arrays and methods utilizing flexible and stretchable LED arrays. Assembly of flexible LED arrays alongside flexible plasmonic crystals is useful for construction of fluid monitors, permitting sensitive detection of fluid refractive index and composition. Co-integration of flexible LED arrays with flexible photodetector arrays is useful for construction of flexible proximity sensors. Application of stretchable LED arrays onto flexible threads as light emitting sutures provides novel means for performing radiation therapy on wounds.

摘要翻译： 这里描述的是柔性和可拉伸的LED阵列和利用灵活和可拉伸的LED阵列的方法。 柔性LED阵列与柔性等离子体激元晶体的组装可用于构建流体监视器，允许灵敏检测流体折射率和组成。 柔性LED阵列与柔性光电探测器阵列的协整集成对于柔性接近传感器的构造是有用的。 将可拉伸LED阵列应用于柔性线作为发光缝线提供了对伤口进行辐射治疗的新颖手段。

公开(公告)号：US20080185624A1

公开(公告)日：2008-08-07

申请号：US12100042

申请日：2008-04-09

申请人： Rak-Hwan Kim ,  Young-Joo Cho ,  Sung-Tae Kim ,  In-Sun Park ,  Hyeon-Deok Lee ,  Hyun-Suk Lee ,  Jung-Hee Chung ,  Hyun-Young Kim ,  Hyun-Seok Lim

发明人： Rak-Hwan Kim ,  Young-Joo Cho ,  Sung-Tae Kim ,  In-Sun Park ,  Hyeon-Deok Lee ,  Hyun-Suk Lee ,  Jung-Hee Chung ,  Hyun-Young Kim ,  Hyun-Seok Lim

IPC分类号： H01L29/94

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/75

摘要： Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening there through on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to form a recess above the contact plug, forming a titanium layer on a bottom surface and side surfaces of the recess, forming a titanium nitride layer on the titanium layer, and forming a titanium oxide nitride layer on the titanium nitride layer. A storage capacitor includes a semiconductor substrate, an interlayer insulation layer having a contact plug therein on the substrate, and a storage electrode on the contact plug including a titanium silicide layer, a titanium nitride layer on the titanium silicide layer, and a titanium oxide nitride layer on the titanium nitride layer.

摘要翻译： 形成存储电容器的方法包括在半导体衬底上形成具有开口的层间绝缘层，在开口中形成接触插塞，在层间绝缘层和接触插塞上形成模制氧化物层，选择性地去除部分 模制氧化物层以在接触塞上方形成凹陷，在凹陷的底表面和侧表面上形成钛层，在钛层上形成氮化钛层，并在氮化钛层上形成氮氧化钛层。 存储电容器包括半导体衬底，在衬底上具有接触插塞的层间绝缘层，以及包括钛硅化物层的接触插塞上的存储电极，硅化钛层上的氮化钛层和氧化钛氮化物 层在氮化钛层上。

公开(公告)号：US20070026671A1

公开(公告)日：2007-02-01

申请号：US11476793

申请日：2006-06-29

申请人： Rak-Hwan Kim ,  Young-Cheon Kim

发明人： Rak-Hwan Kim ,  Young-Cheon Kim

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76877

摘要： Provided is a method for forming low resistance metal films in which an underlying film, for example, a barrier layer or an adhesion layer, is formed on a semiconductor substrate. The underlying film is then subjected to a partial etch back in order to reduce the surface roughness and form a deposition surface. A metal film, for example, a tungsten film, is then formed on a deposition surface that has been formed on the underlying film. Forming the metal film on the deposition surface that has reduced surface roughness will tend to produce a metal film having a larger average grain size and, consequently, a lower sheet resistivity for a given film thickness.

摘要翻译： 提供一种形成低电阻金属膜的方法，其中在半导体衬底上形成底层膜，例如阻挡层或粘附层。 然后对底层膜进行部分回蚀，以减少表面粗糙度并形成沉积表面。 然后在已经形成在下面的膜上的沉积表面上形成金属膜，例如钨膜。 在沉积表面上形成具有降低的表面粗糙度的金属膜将倾向于产生具有较大平均晶粒尺寸的金属膜，并因此产生给定膜厚度的较低的薄层电阻率。

公开(公告)号：US20160293484A1

公开(公告)日：2016-10-06

申请号：US15000302

申请日：2016-01-19

申请人： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

发明人： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

IPC分类号： H01L21/768

CPC分类号： H01L21/76882 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238

摘要： In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

摘要翻译： 在形成布线结构的方法中，在基板上形成下部结构。 在下部结构上形成绝缘中间层。 部分去除绝缘中间层以形成至少一个通孔和虚拟通孔。 绝缘中间层的上部被部分地去除以形成连接通孔和虚拟通孔的沟槽。 形成填充通孔和虚拟通孔的第一金属层。 填充沟槽的第二金属层形成在第一金属层上。

公开(公告)号：US20160276267A1

公开(公告)日：2016-09-22

申请号：US15018484

申请日：2016-02-08

申请人： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Nae-In Lee ,  Jeong-Ok Cha ,  Jung-Ha Hwang

发明人： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Nae-In Lee ,  Jeong-Ok Cha ,  Jung-Ha Hwang

IPC分类号： H01L23/522 ,  H01L21/285 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/53238

摘要： Methods of forming wiring structures and methods of manufacturing semiconductor devices include forming a lower structure on a substrate, forming an interlayer insulating film including an opening on the lower structure, forming a liner film on an inner surface of the opening, treating a surface of the liner film by an ion bombardment, and forming a first conductive film on the liner film. The first conductive film is formed to be at least partially filled in the opening through a reflow process. Related wiring structures and semiconductor devices are also discussed.

摘要翻译： 形成布线结构的方法和制造半导体器件的方法包括在基板上形成下部结构，在下部结构上形成包括开口的层间绝缘膜，在开口的内表面上形成衬垫膜， 通过离子轰击形成衬垫膜，并在衬垫膜上形成第一导电膜。 第一导电膜通过回流工艺形成为至少部分地填充在开口中。 还讨论了相关的布线结构和半导体器件。

公开(公告)号：US07524724B2

公开(公告)日：2009-04-28

申请号：US11173771

申请日：2005-06-30

申请人： Rak-Hwan Kim ,  Hyun-Seok Lim ,  Young-Joo Cho ,  In-Sun Park ,  Hyeon-Deok Lee ,  Hyun-Suk Lee

发明人： Rak-Hwan Kim ,  Hyun-Seok Lim ,  Young-Joo Cho ,  In-Sun Park ,  Hyeon-Deok Lee ,  Hyun-Suk Lee

IPC分类号： H01L21/20

CPC分类号： C23C16/45529 ,  C23C16/34 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91

摘要： A method of fabricating a storage capacitor includes depositing a first titanium nitride layer on a dielectric layer using a chemical vapor deposition technique or an atomic layer deposition technique performed at a first temperature with reactant gases of titanium chloride (TiCl4) gas and ammonia (NH3) gas at a predetermined flow ratio and depositing a second titanium nitride layer on the first titanium nitride layer using a chemical vapor deposition process performed at a second temperature that is greater than the first temperature with reactant gases of titanium chloride (TiCl4) gas and ammonia (NH3) gas.

摘要翻译： 一种制造存储电容器的方法包括使用化学气相沉积技术或在第一温度下用氯化钛（TiCl 4）气体和氨（NH 3））的反应气体进行的原子层沉积技术在电介质层上沉积第一氮化钛层， 气体以预定的流量比并且在第二氮化钛层上沉积第二氮化钛层，所述化学气相沉积工艺是在第二温度下用氯化钛（TiCl 4）气体和氨的反应气体 NH3）气体。

公开(公告)号：US07504725B2

公开(公告)日：2009-03-17

申请号：US10915871

申请日：2004-08-09

申请人： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

发明人： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76876 ,  H01L27/10885 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.

摘要翻译： 一种半导体存储器件和半导体存储器件的制造方法，其中位线可以具有低电阻而不增加位线的厚度。 在半导体存储器件中，在具有导电区域的半导体衬底上形成具有暴露导电区域的接触孔的绝缘层。 沿着绝缘层的表面和接触孔的表面形成阻挡金属层。 在阻挡金属层与钨层之间形成晶粒控制层。 在晶粒控制层上形成钨层。 钨层的晶粒尺寸由晶粒控制层增加。

公开(公告)号：US20070264821A1

公开(公告)日：2007-11-15

申请号：US11785305

申请日：2007-04-17

申请人： Ju-Youn Kim ,  Seok-Jun Won ,  Rak-Hwan Kim ,  Min-Woo Song ,  Weon-Hong Kim ,  Jung-Min Park

发明人： Ju-Youn Kim ,  Seok-Jun Won ,  Rak-Hwan Kim ,  Min-Woo Song ,  Weon-Hong Kim ,  Jung-Min Park

IPC分类号： H01L21/44

CPC分类号： H01L21/32051 ,  H01L28/75

摘要： A method of forming a semiconductor device may include forming a first conductive metal compound layer on a substrate using a metal organic chemical vapor deposition (MOCVD) process and/or forming a second conductive metal compound layer on the first conductive metal compound layer using a physical vapor deposition (PVD) process. The first and second conductive metal compound layers may be formed while reducing or preventing the exposure of the first conductive metal compound layer to oxygen atoms, thus reducing degradation of the first conductive metal compound layer.

摘要翻译： 形成半导体器件的方法可以包括：使用金属有机化学气相沉积（MOCVD）工艺在衬底上形成第一导电金属化合物层和/或在第一导电金属化合物层上形成第二导电金属化合物层，使用物理 气相沉积（PVD）工艺。 可以在减少或防止第一导电金属化合物层暴露于氧原子的同时形成第一和第二导电金属化合物层，从而减少第一导电金属化合物层的劣化。

公开(公告)号：US20050042829A1

公开(公告)日：2005-02-24

申请号：US10915871

申请日：2004-08-09

申请人： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

发明人： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485

CPC分类号： H01L23/485 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76876 ,  H01L27/10885 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.

摘要翻译： 一种半导体存储器件和半导体存储器件的制造方法，其中位线可以具有低电阻而不增加位线的厚度。 在半导体存储器件中，在具有导电区域的半导体衬底上形成具有暴露导电区域的接触孔的绝缘层。 沿着绝缘层的表面和接触孔的表面形成阻挡金属层。 在阻挡金属层与钨层之间形成晶粒控制层。 在晶粒控制层上形成钨层。 钨层的晶粒尺寸由晶粒控制层增加。