公开(公告)号：US20090236697A1

公开(公告)日：2009-09-24

申请号：US12403881

申请日：2009-03-13

申请人： Syotaro ONO ,  Wataru SAITO ,  Nana HATANO ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Miho WATANABE

发明人： Syotaro ONO ,  Wataru SAITO ,  Nana HATANO ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Miho WATANABE

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L29/66712 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7395 ,  H01L29/7811

摘要： A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.

摘要翻译： 半导体器件包括具有交替设置在半导体衬底上的第一导电型第一半导体柱区域和第二导电型第二半导体柱区域的超结区域。 终端区域中的第一半导体柱区域和第二半导体柱区域具有由半导体衬底的顶表面上的第一半导体柱区域和第二半导体柱区域的交替层叠形成的叠层形式。 终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域显示杂质浓度分布，使得多个杂质浓度峰值周期性出现。 终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域具有使得随着角部更靠近圆周而变小的杂质量。

公开(公告)号：US20100038712A1

公开(公告)日：2010-02-18

申请号：US12540192

申请日：2009-08-12

申请人： Miho WATANABE ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Wataru SAITO ,  Syotaro ONO ,  Nana HATANO

发明人： Miho WATANABE ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Wataru SAITO ,  Syotaro ONO ,  Nana HATANO

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7802

摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.

摘要翻译： 根据本发明实施例的半导体器件包括器件部分和端子部分。 该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层 区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB） 从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系 的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

公开(公告)号：US20080315297A1

公开(公告)日：2008-12-25

申请号：US12144985

申请日：2008-06-24

申请人： Masakatsu TAKASHITA ,  Yasuto SUMI ,  Masaru IZUMISAWA ,  Hiroshi OHTA ,  Wataru SAITO ,  Syotaro ONO

发明人： Masakatsu TAKASHITA ,  Yasuto SUMI ,  Masaru IZUMISAWA ,  Hiroshi OHTA ,  Wataru SAITO ,  Syotaro ONO

IPC分类号： H01L29/78

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/402 ,  H01L29/66712 ,  H01L29/7811

摘要： There is provided a semiconductor device having a drift layer with a pillar structure including first semiconductor layer portions of the first conduction type and second semiconductor layer portions of the second conduction type formed in pillars alternately and periodically on a semiconductor substrate. A device region includes a plurality of arrayed transistors composed of the first semiconductor layer portions and the second semiconductor layer portions. A terminal region is formed at the periphery of the device region without the transistors formed therein. The drift layer in the terminal region has a carrier lifetime lower than ⅕ the carrier lifetime in the drift layer in the device region.

摘要翻译： 提供一种具有柱状结构的漂移层的半导体器件，其包括第一导电类型的第一半导体层部分和第二导电类型的第二半导体层部分在半导体衬底上交替周期地形成为柱状。 器件区域包括由第一半导体层部分和第二半导体层部分组成的多个阵列晶体管。 端子区域形成在器件区域的外围，而不形成晶体管。 端子区域中的漂移层的载流子寿命低于器件区域漂移层中的载流子寿命的1/5。

公开(公告)号：US20100187598A1

公开(公告)日：2010-07-29

申请号：US12641831

申请日：2009-12-18

申请人： Koichi ENDO ,  Masaru IZUMISAWA ,  Takuma HARA ,  Syotaro ONO ,  Yoshiro BABA

发明人： Koichi ENDO ,  Masaru IZUMISAWA ,  Takuma HARA ,  Syotaro ONO ,  Yoshiro BABA

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L29/7394 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66325

摘要： There is provided a semiconductor device having a switching element, including a first semiconductor layer including a first, second and third surfaces, a first electrode connected to the first semiconductor layer, a plurality of second semiconductor layers selectively configured on the first surface, a third semiconductor layer configured on the second semiconductor layer, a second electrode configured to be contacted with the second semiconductor layer and the third semiconductor layer, a gate electrode formed over the first semiconductor layer, a first region including a first tale region, a density distribution of crystalline defects being gradually increased therein, a peak region crossing a current path applying to a forward direction in a p-n junction, a second tale region continued from the peak region, and a second region including a third tale region, the density distribution of the crystalline defects being gradually increased therein.

摘要翻译： 提供了一种具有开关元件的半导体器件，包括：第一半导体层，包括第一，第二和第三表面;连接到第一半导体层的第一电极，选择性地配置在第一表面上的多个第二半导体层， 配置在所述第二半导体层上的半导体层，被配置为与所述第二半导体层和所述第三半导体层接触的第二电极，形成在所述第一半导体层上的栅电极，包括第一区段的第一区域， 晶体缺陷在其中逐渐增加，在pn结中穿过施加到正向电流路径的峰值区域，从峰值区域继续的第二段区域和包括第三区域的第二区域，晶体的密度分布 缺陷在其中逐渐增加。