公开(公告)号：US10741665B2

公开(公告)日：2020-08-11

申请号：US16101065

申请日：2018-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Wei Yao ,  Chen-Ju Yu ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/417 ,  H01L29/43 ,  H01L29/778 ,  H01L29/10 ,  H01L29/267 ,  H01L21/02

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

公开(公告)号：US09871030B2

公开(公告)日：2018-01-16

申请号：US15357308

申请日：2016-11-21

Applicant: Taiwan Semiconductor Manufacturing Company, LTD.

Inventor： King-Yuen Wong ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Fu-Wei Yao ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Po-Chih Chen

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8258 ,  H01L23/522 ,  H01L29/205 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/26513 ,  H01L21/26546 ,  H01L21/30612 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/8252 ,  H01L21/8258 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

公开(公告)号：US09224829B2

公开(公告)日：2015-12-29

申请号：US14267954

申请日：2014-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： King-Yuen Wong ,  Chen-Ju Yu ,  Fu-Wei Yao ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Po-Chih Chen ,  Chun-Wei Hsu

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L27/146 ,  H01L29/423 ,  H01L29/778 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L27/14689 ,  H01L29/1033 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42364 ,  H01L29/7787

Abstract: A method of forming a semiconductor structure, the method includes epitaxially growing a second III-V compound layer on a first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. The method further includes forming a source feature and a drain feature on the second III-V compound layer, forming a third III-V compound layer on the second III-V compound layer, depositing a gate dielectric layer on a portion of the second III-V compound layer and a top surface of the third III-V compound layer, treating the gate dielectric layer on the portion of the second III-V compound layer with fluorine and forming a gate electrode on the treated gate dielectric layer between the source feature and the drain feature.

Abstract translation: 一种形成半导体结构的方法，所述方法包括在第一III-V化合物层上外延生长第二III-V化合物层。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 该方法还包括在第二III-V化合物层上形成源特征和漏极特征，在第二III-V化合物层上形成第三III-V化合物层，在第二III -V化合物层和第三III-V化合物层的顶表面，用氟处理第二III-V化合物层的部分上的栅极电介质层，并在处理的栅极电介质层上在源特征 和排水功能。

公开(公告)号：US20150325679A1

公开(公告)日：2015-11-12

申请号：US14790588

申请日：2015-07-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： King-Yuen Wong ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Fu-Wei Yao ,  Fu-Chih Yang

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/308 ,  H01L29/423 ,  H01L29/40 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L29/66462 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/28264 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41716 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66621 ,  H01L29/7786 ,  H01L29/7787

Abstract: An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.

Abstract translation: 集成电路器件包括第一III-V化合物层，第一III-V化合物层上的第二III-V化合物层，第二III-V化合物层上的栅极电介质，以及栅极电介质上的栅电极。 阳极电极和阴极电极形成在栅电极的相对侧上。 阳极电极与栅电极电连接。 阳极电极，阴极电极和栅电极形成整流器的部分。

公开(公告)号：US10020361B2

公开(公告)日：2018-07-10

申请号：US15201130

申请日：2016-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Ju Yu ,  Chih-Wen Hsiung ,  Fu-Wei Yao ,  Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang

IPC: H01L29/788 ,  H01L29/06 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/205 ,  H01L21/306

CPC classification number: H01L29/0661 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/30621 ,  H01L21/3065 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

Abstract: A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain.

公开(公告)号：US09985103B2

公开(公告)日：2018-05-29

申请号：US15362465

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Wei Yao ,  Chen-Ju Yu ,  King-Yuen Wong ,  Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Chun-Lin Tsai

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L21/285 ,  H01L29/417 ,  H01L29/778 ,  H01L29/08

CPC classification number: H01L29/452 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/28575 ,  H01L29/0843 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

公开(公告)号：US20170338316A1

公开(公告)日：2017-11-23

申请号：US15670135

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Wei Yao ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Chih-Wen Hsiung ,  King-Yuen Wong

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.

公开(公告)号：US09502311B2

公开(公告)日：2016-11-22

申请号：US14872197

申请日：2015-10-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： King-Yuen Wong ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Fu-Wei Yao ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Po-Chih Chen

IPC: H01L29/778 ,  H01L21/8252 ,  H01L29/66 ,  H01L29/10 ,  H01L27/06 ,  H01L27/02 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/26513 ,  H01L21/26546 ,  H01L21/30612 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/8252 ,  H01L21/8258 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

Abstract translation: 提供了其上设置III-V化合物层的硅衬底。 通过离子注入工艺在硅衬底中形成二极管。 二极管形成在硅衬底和III-V化合物层之间的界面附近。 通过III-V化合物层蚀刻开口以暴露二极管。 开口填充有导电材料。 由此，形成与二极管耦合的通孔。 至少部分地在III-V化合物层中形成高电子迁移率晶体管（HEMT）器件。

公开(公告)号：US09412835B2

公开(公告)日：2016-08-09

申请号：US14790588

申请日：2015-07-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： King-Yuen Wong ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Fu-Wei Yao ,  Fu-Chih Yang

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423 ,  H01L29/40 ,  H01L21/28 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/28264 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41716 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66621 ,  H01L29/7786 ,  H01L29/7787

Abstract: An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.

公开(公告)号：US08884308B2

公开(公告)日：2014-11-11

申请号：US13650610

申请日：2012-10-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Ju Yu ,  Chih-Wen Hsiung ,  Fu-Wei Yao ,  Chun-Wei Hsu ,  King-Yuen Wong ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L21/2258 ,  H01L21/3065 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.

Abstract translation: 高电子迁移率晶体管（HEMT）包括硅衬底，硅衬底上的无意掺杂的氮化镓（UID GaN）层。 HEMT还包括在供体层上的UID GaN层上的施主供体层，栅极结构，漏极和源极。 HEMT还包括在供体供体层中具有一个或多个电介质塞部分的电介质层和在供体层上的栅极结构和漏极之间的顶部。 还提供了制造HEMT的方法。