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公开(公告)号：US09725310B2
公开(公告)日：2017-08-08
申请号：US14135615
申请日：2013-12-20
Inventor： Chun-wen Cheng , Hung-Chia Tsai , Lan-Lin Chao , Yuan-Chih Hsieh , Ping-Yin Liu
CPC classification number: B81C1/00246 , B81B2201/0242
Abstract: A micro electromechanical system (MEMS) device includes a MEMS section attached to a substrate, and a cap bonded to a first surface of the substrate. The MEMS device further includes a carrier bonded to a second surface of the substrate opposite the first surface, wherein the carrier is free of active devices, and the cap and the carrier define a vacuum region surrounding the MEMS section. The MEMS device further includes a bond pad on a surface of the carrier opposite the MEMS section, wherein the bond pad is electrically connected to the MEMS section.
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公开(公告)号：US11014805B2
公开(公告)日：2021-05-25
申请号：US16544234
申请日：2019-08-19
Inventor： Chun-wen Cheng , Hung-Chia Tsai , Lan-Lin Chao , Yuan-Chih Hsieh , Ping-Yin Liu
IPC: B81C1/00
Abstract: A method of making a semiconductor package includes bonding a carrier to a surface of the substrate, wherein the carrier is free of active devices, wherein the carrier includes a carrier bond pad on a surface of the carrier. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad, wherein the bonding of the wafer bond pad to the carrier bond pad comprises re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.
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公开(公告)号：US20160157038A1
公开(公告)日：2016-06-02
申请号：US15018625
申请日：2016-02-08
Inventor： Jung-Huei Peng , Chia-Hua Chu , Chun-wen Cheng , Chin-Yi Cho , Li-Min Hung , Yao-Te Huang
CPC classification number: H04R31/003 , B81C1/00158 , B81C2201/0125 , B81C2201/013 , B81C2201/053 , B81C2203/036 , H04R19/005 , H04R19/04 , H04R31/006 , H04R2201/003 , H04R2307/027
Abstract: The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.
Abstract translation: 本公开提供了集成麦克风结构的一个实施例。 集成麦克风结构包括图案化为第一板的第一硅衬底。 形成在第一硅衬底的一侧上的氧化硅层。 第二硅衬底通过氧化硅层与第一衬底结合，使得氧化硅层夹在第一和第二硅衬底之间。 一个膜片，其固定在氧化硅层上并且设置在第一和第二硅衬底之间，使得第一板和隔膜被配置成形成电容式麦克风。
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公开(公告)号：US09355896B2
公开(公告)日：2016-05-31
申请号：US14815071
申请日：2015-07-31
Inventor： Chia-Pao Shu , Chun-wen Cheng , Kuei-Sung Chang , Hsin-Ting Huang , Shang-Ying Tsai , Jung-Huei Peng
IPC: H01L23/48 , H01L21/768 , H01L23/58 , H01L23/498 , H01L23/528 , H01L23/00 , B81C1/00 , H01L25/065
CPC classification number: H01L21/76838 , B81C1/00238 , B81C1/00269 , B81C2203/019 , H01L23/49838 , H01L23/528 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/83 , H01L24/94 , H01L25/0657 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/0362 , H01L2224/04026 , H01L2224/05551 , H01L2224/05555 , H01L2224/05557 , H01L2224/05617 , H01L2224/05638 , H01L2224/061 , H01L2224/08145 , H01L2224/08225 , H01L2224/26145 , H01L2224/29011 , H01L2224/29014 , H01L2224/29017 , H01L2224/2902 , H01L2224/291 , H01L2224/29101 , H01L2224/29111 , H01L2224/29117 , H01L2224/29124 , H01L2224/29138 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29181 , H01L2224/301 , H01L2224/32058 , H01L2224/321 , H01L2224/32106 , H01L2224/32148 , H01L2224/83203 , H01L2224/83365 , H01L2224/83805 , H01L2225/06527 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01079 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/01014 , H01L2924/01037 , H01L2924/01032 , H01L2924/00 , H01L2924/0132 , H01L2924/00014
Abstract: A package system includes a first substrate; and a second substrate electrically coupled with the first substrate. The package system further includes a semiconductor material between the first substrate and the second substrate. The semiconductor material includes a pad, and at least one guard ring surrounding the pad and spaced from the pad. The package system further includes a metallic material bonded to the semiconductor material, wherein the metallic material at least partially fills at least one opening in at least one of the first substrate or the second substrate.
Abstract translation: 包装系统包括第一基板; 以及与所述第一基板电耦合的第二基板。 封装系统还包括在第一衬底和第二衬底之间的半导体材料。 半导体材料包括焊盘和围绕焊盘并与焊盘间隔开的至少一个保护环。 封装系统还包括结合到半导体材料的金属材料，其中金属材料至少部分地填充至少一个第一衬底或第二衬底中的一个开口。
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5.发明申请公开(公告)号：US20150076710A1
公开(公告)日：2015-03-19
申请号：US14551874
申请日：2014-11-24
Inventor： Kuei-Sung Chang , Chun-wen Cheng , Alexander Kalnitsky , Chia-Hua Chu
CPC classification number: H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/64 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/80 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/08145 , H01L2224/13022 , H01L2224/13124 , H01L2224/13147 , H01L2224/24011 , H01L2224/24051 , H01L2224/24105 , H01L2224/24145 , H01L2224/80896 , H01L2224/81 , H01L2224/821 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/00014 , H01L2924/01322 , H01L2924/1205 , H01L2924/1305 , H01L2924/13091 , H01L2924/15787 , H01L2924/00 , H01L2224/82 , H05K3/4661 , H01L2224/05552 , H01L2224/8203 , H01L2224/80001
Abstract: The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.
Abstract translation: 本公开提供了堆叠半导体器件的一个实施例。 叠层半导体器件包括第一衬底; 第一衬底上的第一接合焊盘; 第二基板，包括在其上制造的第二电气装置; 在所述第二基板上方的所述第二电气装置上的第二接合焊盘，所述第二接合焊盘电连接到所述第二电气装置; 所述第二接合焊盘上的第二绝缘层具有顶表面，所述第二绝缘层朝向所述第一基板的所述第一接合焊盘接合; 以及从第一接合焊盘相反的表面穿过第一基板延伸并穿过第二绝缘层的顶表面延伸到第二接合焊盘的贯通基板通孔（“TSV”）。
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Patent Agency Ranking
公开(公告)号：US09998843B2
公开(公告)日：2018-06-12
申请号：US15018625
申请日：2016-02-08
Inventor： Jung-Huei Peng , Chia-Hua Chu , Chun-wen Cheng , Chin-Yi Cho , Li-Min Hung , Yao-Te Huang
CPC classification number: H04R31/003 , B81C1/00158 , B81C2201/0125 , B81C2201/013 , B81C2201/053 , B81C2203/036 , H04R19/005 , H04R19/04 , H04R31/006 , H04R2201/003 , H04R2307/027
Abstract: The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.
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公开(公告)号：US09617143B2
公开(公告)日：2017-04-11
申请号：US14585634
申请日：2014-12-30
Inventor： Chun-wen Cheng , Jung-Huei Peng , Shang-Ying Tsai , Hung-Chia Tsai , Yi-Chuan Teng
CPC classification number: B81B7/007 , B81B7/02 , B81B7/04 , B81C1/00214 , B81C1/0023 , B81C1/00333 , H01L2224/11
Abstract: A method of forming a semiconductor device comprises bonding a capping wafer and a base wafer to form a wafer package. The base wafer comprises a plurality of chip package portions. The capping wafer comprises a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is configured to substantially align with a corresponding chip package portion of the plurality of chip package portions. The method also comprises separating the wafer package into a plurality of chip packages. Each chip package of the plurality of chip packages comprises at least one chip package portion of the plurality of chip package portions.
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8.发明授权公开(公告)号：US09293431B2
公开(公告)日：2016-03-22
申请号：US14551874
申请日：2014-11-24
Inventor： Kuei-Sung Chang , Chun-wen Cheng , Alexander Kalnitsky , Chia-Hua Chu
IPC: H01L23/48 , H01L23/00 , H01L25/065 , H01L23/64 , H01L25/16 , H01L25/00 , H01L21/768
CPC classification number: H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/64 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/80 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/08145 , H01L2224/13022 , H01L2224/13124 , H01L2224/13147 , H01L2224/24011 , H01L2224/24051 , H01L2224/24105 , H01L2224/24145 , H01L2224/80896 , H01L2224/81 , H01L2224/821 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/00014 , H01L2924/01322 , H01L2924/1205 , H01L2924/1305 , H01L2924/13091 , H01L2924/15787 , H01L2924/00 , H01L2224/82 , H05K3/4661 , H01L2224/05552 , H01L2224/8203 , H01L2224/80001
Abstract: The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.
Abstract translation: 本公开提供了堆叠半导体器件的一个实施例。 叠层半导体器件包括第一衬底; 第一衬底上的第一接合焊盘; 第二基板，包括在其上制造的第二电气装置; 在所述第二基板上方的所述第二电气装置上的第二接合焊盘，所述第二接合焊盘电连接到所述第二电气装置; 所述第二接合焊盘上的第二绝缘层具有顶表面，所述第二绝缘层朝向所述第一基板的所述第一接合焊盘接合; 以及从第一接合焊盘相反的表面穿过第一基板延伸并穿过第二绝缘层的顶表面延伸到第二接合焊盘的贯通基板通孔（“TSV”）。
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9.发明授权公开(公告)号：US09006015B2
公开(公告)日：2015-04-14
申请号：US13749033
申请日：2013-01-24
Inventor： Chia-Hua Chu , Te-Hao Lee , Jiou-Kang Lee , Kai-Chih Liang , Chung-Hsien Lin , Chun-wen Cheng
CPC classification number: B81C1/00269 , B81B2201/0235 , B81B2201/0242 , B81B2201/0257 , B81B2203/0307 , B81B2207/012 , B81C1/00039 , B81C1/00261 , B81C2203/035
Abstract: Exemplary microelectromechanical system (MEMS) devices, and methods for fabricating such are disclosed. An exemplary method includes providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes a first silicon layer separated from a second silicon layer by an insulator layer; processing the first silicon layer to form a first structure layer of a MEMS device; bonding the first structure layer to a substrate; and processing the second silicon layer to form a second structure layer of the MEMS device.
Abstract translation: 公开了示例性微机电系统（MEMS）装置及其制造方法。 一种示例性方法包括提供绝缘体上硅（SOI）衬底，其中SOI衬底包括通过绝缘体层与第二硅层分离的第一硅层; 处理所述第一硅层以形成MEMS器件的第一结构层; 将第一结构层接合到基板上; 以及处理所述第二硅层以形成所述MEMS器件的第二结构层。
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公开(公告)号：US10779100B2
公开(公告)日：2020-09-15
申请号：US16001032
申请日：2018-06-06
Inventor： Jung-Huei Peng , Chia-Hua Chu , Chun-wen Cheng , Chin-Yi Cho , Li-Min Hung , Yao-Te Huang
Abstract: An embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.
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