公开(公告)号：US10741665B2

公开(公告)日：2020-08-11

申请号：US16101065

申请日：2018-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Wei Yao ,  Chen-Ju Yu ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/417 ,  H01L29/43 ,  H01L29/778 ,  H01L29/10 ,  H01L29/267 ,  H01L21/02

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

公开(公告)号：US09871030B2

公开(公告)日：2018-01-16

申请号：US15357308

申请日：2016-11-21

Applicant: Taiwan Semiconductor Manufacturing Company, LTD.

Inventor： King-Yuen Wong ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Fu-Wei Yao ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Po-Chih Chen

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8258 ,  H01L23/522 ,  H01L29/205 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/26513 ,  H01L21/26546 ,  H01L21/30612 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/8252 ,  H01L21/8258 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

公开(公告)号：US09793385B2

公开(公告)日：2017-10-17

申请号：US15191745

申请日：2016-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ker-Hsiao Huo ,  Fu-Chih Yang ,  Jen-Hao Yeh ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ru-Yi Su

IPC: H01L29/66 ,  H01L29/739 ,  H01L21/265 ,  H01L21/762 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7394 ,  H01L21/26533 ,  H01L21/76243 ,  H01L21/76283 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66325 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

公开(公告)号：US09660108B2

公开(公告)日：2017-05-23

申请号：US14932465

申请日：2015-11-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker-Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/80 ,  H01L29/808 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L27/098

CPC classification number: H01L29/808 ,  H01L27/088 ,  H01L27/098 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/66901

Abstract: A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.

公开(公告)号：US20160336314A1

公开(公告)日：2016-11-17

申请号：US15224263

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Yen Chou ,  Sheng-De Liu ,  Fu-Chih Yang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/088 ,  H01L27/06 ,  H01L29/778 ,  H01L29/20 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8252 ,  H01L29/10

CPC classification number: H01L27/088 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7786

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

公开(公告)号：US09385178B2

公开(公告)日：2016-07-05

申请号：US14179623

申请日：2014-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/02 ,  H01L49/02 ,  H01L29/66 ,  H01L21/761 ,  H01L27/08 ,  H01L29/8605 ,  H01L29/868 ,  H01L29/06 ,  H01L27/06

CPC classification number: H01L29/0649 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/761 ,  H01L21/76202 ,  H01L23/528 ,  H01L27/0676 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/6609 ,  H01L29/8605 ,  H01L29/868

Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Abstract translation: 提供一种高压半导体器件，其包括形成在衬底中的PIN二极管结构。 PIN二极管包括位于第一掺杂阱和第二掺杂阱之间的本征区。 第一和第二掺杂阱具有与内部区域相反的掺杂极性和更大的掺杂浓度水平。 半导体器件包括形成在第一掺杂阱的一部分上的绝缘结构。 半导体器件包括形成在绝缘结构上的细长电阻器件。 电阻器件分别设置在电阻器件的相对端处的第一和第二部分。 半导体器件包括形成在电阻器件上的互连结构。 互连结构包括：电耦合到第一掺杂阱的第一接触和电耦合到位于第一和第二部分之间的电阻器的第三部分的第二接触。

公开(公告)号：US09224829B2

公开(公告)日：2015-12-29

申请号：US14267954

申请日：2014-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： King-Yuen Wong ,  Chen-Ju Yu ,  Fu-Wei Yao ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Po-Chih Chen ,  Chun-Wei Hsu

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L27/146 ,  H01L29/423 ,  H01L29/778 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L27/14689 ,  H01L29/1033 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42364 ,  H01L29/7787

Abstract: A method of forming a semiconductor structure, the method includes epitaxially growing a second III-V compound layer on a first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. The method further includes forming a source feature and a drain feature on the second III-V compound layer, forming a third III-V compound layer on the second III-V compound layer, depositing a gate dielectric layer on a portion of the second III-V compound layer and a top surface of the third III-V compound layer, treating the gate dielectric layer on the portion of the second III-V compound layer with fluorine and forming a gate electrode on the treated gate dielectric layer between the source feature and the drain feature.

Abstract translation: 一种形成半导体结构的方法，所述方法包括在第一III-V化合物层上外延生长第二III-V化合物层。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 该方法还包括在第二III-V化合物层上形成源特征和漏极特征，在第二III-V化合物层上形成第三III-V化合物层，在第二III -V化合物层和第三III-V化合物层的顶表面，用氟处理第二III-V化合物层的部分上的栅极电介质层，并在处理的栅极电介质层上在源特征 和排水功能。

公开(公告)号：US20150325679A1

公开(公告)日：2015-11-12

申请号：US14790588

申请日：2015-07-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： King-Yuen Wong ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Fu-Wei Yao ,  Fu-Chih Yang

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/308 ,  H01L29/423 ,  H01L29/40 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L29/66462 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/28264 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41716 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66621 ,  H01L29/7786 ,  H01L29/7787

Abstract: An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.

Abstract translation: 集成电路器件包括第一III-V化合物层，第一III-V化合物层上的第二III-V化合物层，第二III-V化合物层上的栅极电介质，以及栅极电介质上的栅电极。 阳极电极和阴极电极形成在栅电极的相对侧上。 阳极电极与栅电极电连接。 阳极电极，阴极电极和栅电极形成整流器的部分。

公开(公告)号：US20140139282A1

公开(公告)日：2014-05-22

申请号：US14166475

申请日：2014-01-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun-Lin Tsai

IPC: H03K17/22 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/7832 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H03K17/223

Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Abstract translation: 一种器件包括掩埋阱区和第一导电性的第一HVW区，以及位于第一HVW区上的绝缘区。 第一导电类型的漏极区域设置在绝缘区域的第一侧和第一HVW区域的顶表面区域中。 与第一导电类型相反的第二导电类型的第一阱区和第二阱区在绝缘区的第二侧上。 第一导电类型的第二HVW区域设置在第一和第二阱区域之间，其中第二HVW区域连接到掩埋阱区域。 第一导电类型的源极区域位于第二HVW区域的顶表面区域中，其中源极区域，漏极区域和掩埋阱区域形成JFET。

公开(公告)号：US20140057407A1

公开(公告)日：2014-02-27

申请号：US14074435

申请日：2013-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/66

CPC classification number: H01L29/66166 ,  H01L23/5228 ,  H01L27/0288 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.

Abstract translation: 提供一种半导体器件。 半导体器件包括电阻器和电压保护器件。 电阻器具有螺旋形状。 电阻器具有第一部分和第二部分。 电压保护装置包括电耦合到电阻器的第一部分的第一掺杂区域。 电压保护装置包括电耦合到电阻器的第二部分的第二掺杂区域。 第一和第二掺杂区具有相反的掺杂极性。