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公开(公告)号:US20180233406A1
公开(公告)日:2018-08-16
申请号:US15953708
申请日:2018-04-16
发明人: Ching-Fu Yeh , Chao-Hsien Peng , Hsien-Chang Wu , Hsiang-Huan Lee
IPC分类号: H01L21/768 , H01L21/3213 , H01L21/02 , H01L21/027
CPC分类号: H01L21/76892 , B82Y40/00 , H01L21/02115 , H01L21/02697 , H01L21/0271 , H01L21/0273 , H01L21/32135 , H01L21/32139 , H01L21/76838 , H01L21/76885 , H01L21/76897 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , H01L2924/00
摘要: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
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公开(公告)号:US10014175B2
公开(公告)日:2018-07-03
申请号:US15714821
申请日:2017-09-25
发明人: Yu-Sheng Chang , Cheng-Hsiung Tsai , Chung-Ju Lee , Hai-Ching Chen , Hsiang-Huan Lee , Ming-Feng Shieh , Ru-Gun Liu , Shau-Lin Shue , Tien-I Bao , Tsai-Sheng Gau , Yung-Hsu Wu
IPC分类号: H01L21/338 , H01L21/033 , H01L21/02 , H01L21/306 , H01L21/3213
CPC分类号: H01L21/0338 , H01L21/02186 , H01L21/02282 , H01L21/0332 , H01L21/0337 , H01L21/30604 , H01L21/32139
摘要: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
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公开(公告)号:US09818644B2
公开(公告)日:2017-11-14
申请号:US15088134
申请日:2016-04-01
发明人: Shin-Yi Yang , Hsi-Wen Tien , Ming-Han Lee , Hsiang-Huan Lee , Shau-Lin Shue
IPC分类号: H01L23/48 , H01L21/768 , H01L23/532 , H01L23/485 , H01L23/522 , H01L21/285
CPC分类号: H01L21/76879 , H01L21/28556 , H01L21/28562 , H01L21/76816 , H01L21/76844 , H01L21/76876 , H01L21/76883 , H01L23/481 , H01L23/485 , H01L23/5226 , H01L23/53276 , H01L23/53295 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要: The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.
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公开(公告)号:US09646932B2
公开(公告)日:2017-05-09
申请号:US15012147
申请日:2016-02-01
IPC分类号: H01L23/48 , H01L23/532 , H01L21/768 , H01L21/3213 , H01L23/522 , H01L23/528
CPC分类号: H01L23/53238 , H01L21/32133 , H01L21/76805 , H01L21/76849 , H01L21/76867 , H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L23/528 , H01L23/53233 , H01L23/5329 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.
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公开(公告)号:US09490205B2
公开(公告)日:2016-11-08
申请号:US14713179
申请日:2015-05-15
IPC分类号: H01L23/48 , H01L23/522 , H01L23/532 , H01L21/768 , H01L23/528
CPC分类号: H01L23/5226 , H01L21/76802 , H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76885 , H01L23/5222 , H01L23/528 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/00 , H01L2924/0002
摘要: A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.
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公开(公告)号:US09455184B2
公开(公告)日:2016-09-27
申请号:US14496780
申请日:2014-09-25
发明人: Ching-Fu Yeh , Hsiang-Huan Lee
IPC分类号: H01L21/4763 , H01L21/768 , H01L23/532
CPC分类号: H01L21/76885 , H01L21/76807 , H01L21/76819 , H01L21/76843 , H01L21/76846 , H01L21/7685 , H01L21/76855 , H01L21/76858 , H01L21/76882 , H01L21/76883 , H01L21/76886 , H01L21/76892 , H01L23/53219 , H01L23/53223 , H01L23/53295 , H01L2221/1036 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要: A method comprises depositing a first alloy layer over a substrate, depositing a metal layer over the first alloy layer, depositing a second alloy layer over the metal layer, patterning the first alloy layer, the metal layer and the second alloy layer to form a metal structure and depositing a dielectric layer over the metal structure through a chemical vapor deposition (CVD) process.
摘要翻译: 一种方法包括在衬底上沉积第一合金层,在第一合金层上沉积金属层,在金属层上沉积第二合金层,图案化第一合金层,金属层和第二合金层以形成金属 通过化学气相沉积(CVD)工艺在金属结构上沉积介电层。
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公开(公告)号:US09425089B2
公开(公告)日:2016-08-23
申请号:US14319464
申请日:2014-06-30
发明人: Tai-I Yang , Hsiang-Wei Liu , Chia-Tien Wu , Hsiang-Huan Lee , Tien-Lu Lin
IPC分类号: H01L21/768 , H01L21/311 , H01L21/02 , H01L21/3213
CPC分类号: H01L21/76877 , H01L21/02175 , H01L21/02178 , H01L21/02244 , H01L21/02258 , H01L21/0337 , H01L21/31053 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32133 , H01L21/32134 , H01L21/32136 , H01L21/32139 , H01L21/76802 , H01L21/76807 , H01L21/76811 , H01L21/76816 , H01L21/76843
摘要: Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask.
摘要翻译: 公开了导电元件结构及其制造方法。 在一些实施例中,在绝缘层中形成导电元件的方法包括:在设置在绝缘层上的金属层中形成凹陷; 在所述凹部的侧壁上选择性地形成金属衬垫; 并使用金属层和金属衬垫作为掩模在绝缘层中蚀刻通孔。
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8.
公开(公告)号:US20160148874A1
公开(公告)日:2016-05-26
申请号:US15012147
申请日:2016-02-01
IPC分类号: H01L23/532 , H01L21/3213 , H01L21/768 , H01L23/528 , H01L23/522
CPC分类号: H01L23/53238 , H01L21/32133 , H01L21/76805 , H01L21/76849 , H01L21/76867 , H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L23/528 , H01L23/53233 , H01L23/5329 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.
摘要翻译: 形成互连结构的方法包括在半导体衬底上形成电介质材料层。 图案化电介质材料层以在其中形成多个通孔。 第一金属层形成在电介质材料层上,其中第一金属层填充多个通孔。 第一金属层被平坦化,使得其顶部与电介质材料层的顶部共面,以形成多个第一金属特征。 在多个第一金属特征中的每一个的顶部上形成停止层,其中,停止层停止随后的蚀刻以蚀刻到多个第一金属特征中。
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公开(公告)号:US20150126030A1
公开(公告)日:2015-05-07
申请号:US14072890
申请日:2013-11-06
发明人: Shin-Yi Yang , Ching-Fu Yeh , Tz-Jun Kuo , Hsiang-Huan Lee , Ming Han Lee
IPC分类号: H01L21/768
CPC分类号: H01L21/76873 , C25D3/38 , C25D7/123 , H01L21/288 , H01L21/2885 , H01L21/44 , H01L21/76802 , H01L21/76843 , H01L21/76861 , H01L21/76871 , H01L21/76877 , H01L21/76879
摘要: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.
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公开(公告)号:US20140315382A1
公开(公告)日:2014-10-23
申请号:US14322330
申请日:2014-07-02
IPC分类号: H01L21/768
CPC分类号: H01L21/76843 , H01L21/486 , H01L21/76801 , H01L21/76804 , H01L21/76808 , H01L21/76837 , H01L21/76852 , H01L21/76883 , H01L21/76885 , H01L23/5283 , H01L23/53238 , H01L23/5329 , H01L23/538 , H01L2924/0002 , H01L2924/00
摘要: A method of forming a semiconductor device includes forming a plurality of substantially equal-spaced first spacers having a first pitch over a substrate and forming first metal interconnecting wires utilizing the first spacers. The method also includes forming a plurality of substantially equal-spaced second spacers in such a way to abut, respectively, the plurality of first metal interconnecting wires and define a plurality of substantially equal-spaced trenches. A plurality of second metal interconnecting wires are disposed, respectively, within the trenches and the second spacers are removed, thereby defining a plurality of substantially equal-spaced channels.
摘要翻译: 形成半导体器件的方法包括在衬底上形成具有第一间距的多个基本相等间隔的第一间隔物,并且利用第一间隔物形成第一金属互连线。 该方法还包括以这样的方式形成多个基本相等间隔的第二间隔件,以分别邻接多个第一金属互连线并限定多个基本相等间隔的沟槽。 多个第二金属互连线分别设置在沟槽内,并且第二间隔件被移除,从而限定多个基本相等间隔的通道。
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