公开(公告)号：US11594636B2

公开(公告)日：2023-02-28

申请号：US17651437

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Wen-Yen Chen ,  Ying-Lang Wang ,  Liang-Yin Chen ,  Li-Ting Wang ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/324

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

公开(公告)号：US11257952B2

公开(公告)日：2022-02-22

申请号：US16876436

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Wen-Yen Chen ,  Ying-Lang Wang ,  Liang-Yin Chen ,  Li-Ting Wang ,  Huicheng Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/324

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

公开(公告)号：US20190224810A1

公开(公告)日：2019-07-25

申请号：US16025913

申请日：2018-07-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih Hung Chen ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC: B24B37/24 ,  B24B37/04

Abstract: A polishing pad includes a pad layer and one or more polishing structures over an upper surface of the pad layer, where each of the one or more polishing structures has a pre-determined shape and is formed at a pre-determined location of the pad layer, where the one or more polishing structures comprise at least one continuous line shaped segment extending along the upper surface of the pad layer, where each of the one or more polishing structures is a homogeneous material.

公开(公告)号：US20180108836A1

公开(公告)日：2018-04-19

申请号：US15845812

申请日：2017-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/145 ,  H01L45/1608

Abstract: Methods for a resistive random access memory (RRAM) device are disclosed. A bottom electrode is formed over a substrate. A top electrode is formed over the bottom electrode. A resistive switching layer is formed interposed between the top electrode and the bottom electrode. The resistive switching is made of a composite of a metal, Si, and O, formed by oxidation of a metal silicide of a metal, co-deposition of the metal and silicon in oxygen ambiance, co-deposition of a metal oxide of the metal and silicon, or co-deposition of a metal oxide of the metal and silicon oxide. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.

公开(公告)号：US09865731B2

公开(公告)日：2018-01-09

申请号：US14081517

申请日：2013-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-Chih Chen ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L27/12 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/84 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/161 ,  H01L29/6659

Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.

公开(公告)号：US09812492B2

公开(公告)日：2017-11-07

申请号：US14685123

申请日：2015-04-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shiu-Ko JangJian ,  Chi-Cherng Jeng ,  Volume Chien ,  Ying-Lang Wang

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14687 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L31/18

Abstract: A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein an interconnect layer is formed over the first side of the semiconductor substrate, a backside illumination film formed over a second side of the semiconductor substrate, a metal shielding layer formed over the backside illumination film and a via embedded in the backside illumination film and coupled between the metal shielding layer and the semiconductor substrate.

公开(公告)号：US09490345B2

公开(公告)日：2016-11-08

申请号：US14530320

申请日：2014-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-Chih Chen ,  Fu-Tsun Tsai ,  Yung-Fa Lee ,  Ko-Min Lin ,  Chih-Mu Huang ,  Ying-Lang Wang

IPC: H01L29/417 ,  H01L29/45 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285 ,  H01L29/165 ,  H01L21/265 ,  H01L21/768

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.

Abstract translation: 半导体器件包括在衬底上的栅极结构; 与栅极结构相邻的凸起的源极/漏极区域; 以及掺杂区域上的互连插头。 升高的源极/漏极区域包括从衬底的表面升高的顶表面; 以及暴露在顶表面上的掺杂区域。 掺杂区域包括大于凸起源极/漏极区域的任何其它部分的掺杂剂浓度。 互连插头的最底部包括近似于掺杂区域的宽度的宽度。

公开(公告)号：US09252180B2

公开(公告)日：2016-02-02

申请号：US13763355

申请日：2013-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Volume Chien ,  I-Chih Chen ,  Ying-Lang Wang ,  Hsin-Chi Chen ,  Ying-Hao Chen ,  Hung-Ta Huang

IPC: H01L21/00 ,  H01L27/146 ,  H01L23/00 ,  H04N5/335

CPC classification number: H01L27/14636 ,  H01L21/764 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/14 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14683 ,  H01L2224/0401 ,  H01L2224/05075 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08054 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15788 ,  H04N5/335 ,  H01L2924/00

Abstract: A bonding pad structure for an image sensor device and a method of fabrication thereof. The image sensor device has a radiation-sensor region including a substrate and a radiation detection device, and a bonding pad region including the bonding pad structure. The bonding pad structure includes: an interconnect layer; an interlayer dielectric layer (IDL), both layers extending from under the substrate into the bonding pad region; an isolation layer formed on IDL; a conductive pad having a planar portion and one or more bridging portions extending perpendicularly from the planar portion, through the IDL and isolation layers, and to the interconnect layer; and a plurality of non-conducting stress-releasing structures disposed between the isolation layer and the conductive pad in such a way to adjoin its planar and the bridging portions together for releasing potential pulling stress applied thereon and preventing a conductive pad peeling.

Abstract translation: 一种用于图像传感器装置的焊盘结构及其制造方法。 图像传感器装置具有包括基板和放射线检测装置的辐射传感器区域和包括接合焊盘结构的焊盘区域。 接合焊盘结构包括：互连层; 层间电介质层（IDL），从衬底下延伸到焊盘区域的两层; 在IDL上形成隔离层; 具有平面部分和从平面部分垂直延伸穿过IDL和隔离层以及互连层的一个或多个桥接部分的导电焊盘; 以及设置在隔离层和导电焊盘之间的多个非导电应力释放结构，以将其平面和桥接部分邻接在一起，以释放施加在其上的潜在的拉应力并防止导电垫剥离。

公开(公告)号：US20140225215A1

公开(公告)日：2014-08-14

申请号：US13763355

申请日：2013-02-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： VOLUME CHIEN ,  Chen I-Chih ,  Ying-Lang Wang ,  Chen Hsin-Chi ,  Chen Ying-Hao ,  Huang-Ta Huang

IPC: H01L31/02 ,  H01L31/18

CPC classification number: H01L27/14636 ,  H01L21/764 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/14 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14683 ,  H01L2224/0401 ,  H01L2224/05075 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08054 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15788 ,  H04N5/335 ,  H01L2924/00

Abstract: A bonding pad structure for an image sensor device and a method of fabrication thereof. The image sensor device has a radiation-sensor region including a substrate and a radiation detection device, and a bonding pad region including the bonding pad structure. The bonding pad structure includes: an interconnect layer; an interlayer dielectric layer (IDL), both layers extending from under the substrate into the bonding pad region; an isolation layer formed on IDL; a conductive pad having a planar portion and one or more bridging portions extending perpendicularly from the planar portion, through the IDL and isolation layers, and to the interconnect layer; and a plurality of non-conducting stress-releasing structures disposed between the isolation layer and the conductive pad in such a way to adjoin its planar and the bridging portions together for releasing potential pulling stress applied thereon and preventing a conductive pad peeling.

Abstract translation: 一种用于图像传感器装置的焊盘结构及其制造方法。 图像传感器装置具有包括基板和放射线检测装置的辐射传感器区域和包括接合焊盘结构的焊盘区域。 接合焊盘结构包括：互连层; 层间电介质层（IDL），从衬底下延伸到焊盘区域的两层; 在IDL上形成隔离层; 具有平面部分和从平面部分垂直延伸穿过IDL和隔离层以及互连层的一个或多个桥接部分的导电焊盘; 以及设置在隔离层和导电焊盘之间的多个非导电应力释放结构，以将其平面和桥接部分邻接在一起，以释放施加在其上的潜在的拉应力并防止导电垫剥离。

公开(公告)号：US20130334581A1

公开(公告)日：2013-12-19

申请号：US13969370

申请日：2013-08-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen

IPC: H01L29/45 ,  C23C14/14

CPC classification number: H01L29/45 ,  C23C14/14 ,  C23C14/3414 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/823418 ,  H01L29/456 ,  H01L29/665 ,  Y10T29/41

Abstract: A device includes a substrate and a metal-oxide-semiconductor (MOS) device. The MOS device includes a gate dielectric over the substrate, a gate electrode over the gate dielectric, a source/drain region adjacent the gate dielectric, and a source/drain silicide over and contacting the source/drain region. The source/drain silicide comprises silicon, nickel, and a secondary metal. A ratio of a volume percentage of the secondary metal to a volume percentage of the silicon in the source/drain silicide is between about 0.005 and about 0.1. The secondary metal has a density between about 5,000 kg/m3 and about 15,000 kg/m3.

Abstract translation: 一种器件包括衬底和金属氧化物半导体（MOS）器件。 MOS器件包括在衬底上的栅极电介质，在栅极电介质上方的栅极电极，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物，并与源极/漏极区域接触。 源极/漏极硅化物包括硅，镍和二次金属。 源极/漏极硅化物中二次金属的体积百分比与硅的体积百分比的比率在约0.005和约0.1之间。 二次金属具有约5,000kg / m 3至约15,000kg / m 3的密度。