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公开(公告)号：US12127483B2
公开(公告)日：2024-10-22
申请号：US17388484
申请日：2021-07-29
发明人： Bi-Shen Lee , Hai-Dang Trinh , Hsun-Chung Kuang , Cheng-Yuan Tsai
摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
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公开(公告)号：US12102019B2
公开(公告)日：2024-09-24
申请号：US18335176
申请日：2023-06-15
发明人： Hai-Dang Trinh , Chii-Ming Wu , Cheng-Yuan Tsai , Tzu-Chung Tsai , Fa-Shen Jiang
CPC分类号： H10N70/826 , H10N70/021 , H10N70/063 , H10N70/8833 , H10N70/8836 , H10N70/231
摘要： Various embodiments of the present disclosure are directed towards an integrated chip. A first conductive structure overlies a substrate. A second conductive structure overlies the first conductive structure. A data storage structure is disposed between the first and second conductive structures. The data storage structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. Respective bandgaps of the first, second, and third dielectric layers are different from one another.
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公开(公告)号：US12075626B2
公开(公告)日：2024-08-27
申请号：US18332080
申请日：2023-06-09
发明人： Hai-Dang Trinh , Yi Yang Wei , Bi-Shen Lee , Fa-Shen Jiang , Hsun-Chung Kuang , Cheng-Yuan Tsai
摘要： In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion coupling the first lower horizontal portion to the first upper horizontal portion.
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公开(公告)号：US11895933B2
公开(公告)日：2024-02-06
申请号：US17855155
申请日：2022-06-30
发明人： Fa-Shen Jiang , Cheng-Yuan Tsai , Hai-Dang Trinh , Hsing-Lien Lin , Hsun-Chung Kuang , Bi-Shen Lee
CPC分类号： H10N70/828 , H10B63/30 , H10N70/043 , H10N70/063 , H10N70/24 , H10N70/8833
摘要： Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.
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公开(公告)号：US20230320103A1
公开(公告)日：2023-10-05
申请号：US18332080
申请日：2023-06-09
发明人： Hai-Dang Trinh , Yi Yang Wei , Bi-Shen Lee , Fa-Shen Jiang , Hsun-Chung Kuang , Cheng-Yuan Tsai
IPC分类号： H10B53/30
摘要： In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion coupling the first lower horizontal portion to the first upper horizontal portion.
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公开(公告)号：US20230317541A1
公开(公告)日：2023-10-05
申请号：US18331249
申请日：2023-06-08
IPC分类号： H01L23/31 , H01L21/56 , H01L21/768 , H01L23/48 , H01L23/528 , H01L25/065
CPC分类号： H01L23/3185 , H01L21/56 , H01L21/76829 , H01L23/481 , H01L23/5283 , H01L25/0657
摘要： The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.
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公开(公告)号：US11758830B2
公开(公告)日：2023-09-12
申请号：US17324328
申请日：2021-05-19
发明人： Hai-Dang Trinh , Hsing-Lien Lin , Cheng-Yuan Tsai
CPC分类号： H10N70/828 , H10N70/063 , H10N70/24 , H10N70/245 , H10N70/801 , H10N70/826 , H10N70/841 , H10N70/8833
摘要： A semiconductor device structure is provided. The structure includes a semiconductor substrate and a data storage element over the semiconductor substrate. The structure also includes an ion diffusion barrier element over the data storage element and a protective element extending along a sidewall of the ion diffusion barrier element. A bottom surface of the protective element is between a top surface of the data storage element and a bottom surface of the data storage element. The structure further includes a first electrode electrically connected to the data storage element and a second electrode electrically connected to the data storage element.
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公开(公告)号：US11735635B2
公开(公告)日：2023-08-22
申请号：US17305971
申请日：2021-07-19
发明人： Chun-Han Tsao , Chih-Ming Chen , Han-Yu Chen , Szu-Yu Wang , Lan-Lin Chao , Cheng-Yuan Tsai
IPC分类号： H01L29/94 , H01L29/76 , H01L31/119 , H01L29/423 , H01L29/66 , H01L21/28 , H01L21/285 , H01L21/768 , H01L49/02 , H01L21/02 , H10B43/30 , H10B43/40
CPC分类号： H01L29/42344 , H01L21/02063 , H01L21/02068 , H01L21/28052 , H01L21/28518 , H01L21/76834 , H01L21/76856 , H01L28/00 , H01L29/665 , H10B43/30 , H10B43/40
摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
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公开(公告)号：US20230100181A1
公开(公告)日：2023-03-30
申请号：US18076801
申请日：2022-12-07
IPC分类号： G11C11/16 , G11C11/56 , H01L27/11507 , H01L27/22 , H01L27/24
摘要： Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.
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公开(公告)号：US20220393101A1
公开(公告)日：2022-12-08
申请号：US17388484
申请日：2021-07-29
发明人： Bi-Shen Lee , Hai-Dang Trinh , Hsun-Chung Kuang , Cheng-Yuan Tsai
摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
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