-
公开(公告)号：US12302658B2
公开(公告)日：2025-05-13
申请号：US17813947
申请日：2022-07-21
Inventor： Wei-Lin Chen , Yu-Cheng Tsai , Chun-Hao Chou , Kuo-Cheng Lee
Abstract: A semiconductor image sensing structure includes a semiconductor substrate having a front side and a back side, a pixel sensor disposed in the semiconductor substrate, a transistor disposed over the front side of the semiconductor substrate, and a reflective structure disposed over the front side of the semiconductor substrate. A gate structure of the transistor and the reflective structure include a same material. A top surface of the gate structure of the transistor and a top surface of the reflective structure are aligned with each other.
-
公开(公告)号：US12211805B2
公开(公告)日：2025-01-28
申请号：US17447997
申请日：2021-09-17
Inventor： Chun-Liang Lu , Chun-Wei Chia , Chun-Hao Chou , Kuo-Cheng Lee
Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.
-
公开(公告)号：US12081866B2
公开(公告)日：2024-09-03
申请号：US18327825
申请日：2023-06-01
Inventor： Yun-Wei Cheng , Chun-Hao Chou , Hsin-Chi Chen , Kuo-Cheng Lee , Hsun-Ying Huang
IPC: H04N5/232 , H01L27/146 , H04N23/10 , H04N23/67 , H04N25/13 , H04N25/133 , H04N25/702 , H04N25/704 , H04N5/369
CPC classification number: H04N23/67 , H01L27/14603 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14689 , H04N23/10 , H04N25/133 , H04N25/134 , H04N25/702 , H04N25/704
Abstract: An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.
-
公开(公告)号：US11706525B2
公开(公告)日：2023-07-18
申请号：US17493752
申请日：2021-10-04
Inventor： Yun-Wei Cheng , Chun-Hao Chou , Hsin-Chi Chen , Kuo-Cheng Lee , Hsun-Ying Huang
IPC: H04N5/232 , H04N23/67 , H01L27/146 , H04N23/10 , H04N25/133 , H04N25/13 , H04N25/702 , H04N25/704 , H04N5/369
CPC classification number: H04N23/67 , H01L27/1463 , H01L27/14603 , H01L27/14621 , H01L27/14627 , H01L27/14689 , H04N23/10 , H04N25/133 , H04N25/134 , H04N25/702 , H04N25/704
Abstract: An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.
-
公开(公告)号：US20210384233A1
公开(公告)日：2021-12-09
申请号：US17401382
申请日：2021-08-13
Inventor： Yun-Wei Cheng , Horng-Huei Tseng , Chao-Hsiung Wang , Chun-Hao Chou , Tsung-Han Tsai , Kuo-Cheng Lee , Tzu-Hsuan Hsu , Yung-Lung Hsu
IPC: H01L27/146
Abstract: A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.
-
Patent Agency Ranking
公开(公告)号：US09559135B2
公开(公告)日：2017-01-31
申请号：US14464035
申请日：2014-08-20
Inventor： Cheng-Yuan Li , Kun-Huei Lin , Chun-Hao Chou , Kuo-Cheng Lee , Yung-Lung Hsu
IPC: H01L23/48 , H01L27/146 , H01L31/18 , H01L31/02
CPC classification number: H01L27/14636 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14634 , H01L27/1464 , H01L27/1469 , H01L31/02002
Abstract: A semiconductor device includes a first semiconductor chip comprising a first metallic structure and a second semiconductor chip comprising a second metallic structure. The second semiconductor chip is bonded with the first semiconductor chip by a first conductive plug. A second conductive plug extends from the first metallic structure and into a substrate of the first semiconductor chip. The first conductive plug connects the first metallic structure and the second metallic structure, wherein a conductive liner is along a sidewall of the first conductive plug or the second conductive plug.
Abstract translation: 半导体器件包括包括第一金属结构的第一半导体芯片和包括第二金属结构的第二半导体芯片。 第二半导体芯片通过第一导电插塞与第一半导体芯片接合。 第二导电插塞从第一金属结构延伸到第一半导体芯片的衬底中。 第一导电插头连接第一金属结构和第二金属结构，其中导电衬垫沿着第一导电插塞或第二导电插塞的侧壁。
-
公开(公告)号：US09196642B2
公开(公告)日：2015-11-24
申请号：US13708625
申请日：2012-12-07
Inventor： Tsung-Han Tsai , Allen Tseng , Yen-Hsung Ho , Chun-Hao Chou , Kuo-Cheng Lee , Volume Chien , Chi-Cherng Jeng
IPC: H01L27/146 , H01L21/00 , H01L31/18
CPC classification number: H01L27/14636 , H01L27/146 , H01L27/1464 , H01L27/14689 , H01L31/18 , H01L31/1804 , Y02E10/547 , Y02P70/521
Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.
Abstract translation: 一种实施方案的半导体器件包括诸如硅或含硅膜的衬底，由衬底支撑的像素阵列以及围绕像素阵列周围布置的金属应力释放特征。 金属应力释放特征可以由金属条或离散金属元件形成。 金属应力释放特征可以布置在使用单线或多条线的应力释放模式中。 金属应力释放模式也可以在线的端部使用金属角元件。
-
公开(公告)号：US12183753B2
公开(公告)日：2024-12-31
申请号：US17483962
申请日：2021-09-24
Inventor： Wei-Lin Chen , Ching-Chung Su , Chun-Hao Chou , Kuo-Cheng Lee
IPC: H01L27/146 , G02F1/19
Abstract: An image sensor includes a first photodiode and a second photodiode. The image sensor further includes a first color filter over the first photodiode; and a second color filter over the second photodiode. The image sensor further includes a first microlens over the first color filter and a second microlens over the second color filter. The image sensor further includes a first electro-optical (EO) film between the first color filter and the first microlens, wherein a material of the first EO film is configured to change refractive index in response to application of an electrical field. The image sensor further includes a second EO film between the second color filter and the second microlens, wherein a material of the second EO film is configured to change refractive index in response to application of an electrical field.
-
公开(公告)号：US12170234B2
公开(公告)日：2024-12-17
申请号：US18335413
申请日：2023-06-15
Inventor： Chun-Liang Lu , Chun-Wei Chia , Chun-Hao Chou , Kuo-Cheng Lee
Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.
-
公开(公告)号：US20240395785A1
公开(公告)日：2024-11-28
申请号：US18200886
申请日：2023-05-23
Inventor： Ming-Hsien Yang , Chun-Hao Chou , Chia-Yu Wei , Kuo-Cheng Lee , Chung-Liang Cheng , Sheng-Chau Chen
IPC: H01L25/16 , H01L23/00 , H01L27/146
Abstract: A method and wafer stack that includes a first wafer component, a second wafer component, and third wafer component. The first wafer component includes a frontside and a backside. The wafer stack also includes a second wafer component having a frontside and a backside, such that the frontside of the second wafer component is bonded to the frontside of the first wafer component. In addition, the wafer stack includes a third wafer component having a frontside and a backside, such that the frontside of the third wafer component is bonded to the backside of the second wafer component. The first wafer component includes a composite metal grid array with one or more photodiodes formed on the backside.
-
-
-
-
-
-
-
-
-
Search Results
68
records
(took 0.021 seconds)
