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公开(公告)号：US12119238B2
公开(公告)日：2024-10-15
申请号：US16588588
申请日：2019-09-30
Inventor： Meng-Tse Chen , Hsiu-Jen Lin , Wei-Hung Lin , Kuei-Wei Huang , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L21/56 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/10
CPC classification number: H01L21/563 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/06181 , H01L2224/1144 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13111 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13172 , H01L2224/1403 , H01L2224/14181 , H01L2224/14505 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81203 , H01L2224/8123 , H01L2224/81815 , H01L2224/83191 , H01L2224/83192 , H01L2224/83855 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/1023 , H01L2225/1058 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/15787 , H01L2924/181 , H01L2924/15787 , H01L2924/00 , H01L2924/181 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2224/94 , H01L2224/81 , H01L2224/13111 , H01L2924/013 , H01L2924/00014 , H01L2224/13147 , H01L2924/00014 , H01L2224/13166 , H01L2924/00014 , H01L2224/13172 , H01L2924/00014 , H01L2224/13124 , H01L2924/00014 , H01L2224/13155 , H01L2924/00014 , H01L2224/97 , H01L2224/81 , H01L2224/94 , H01L2224/11
Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.
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公开(公告)号：US12119229B2
公开(公告)日：2024-10-15
申请号：US17727606
申请日：2022-04-22
Inventor： Yu-Hsiang Hu , Wei-Yu Chen , Hung-Jui Kuo , Wei-Hung Lin , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L21/304 , H01L23/00 , H01L23/14 , H01L23/15 , H01L23/31 , H01L25/065 , H01L25/07 , H01L21/56
CPC classification number: H01L21/304 , H01L23/147 , H01L23/15 , H01L23/3121 , H01L23/3157 , H01L23/3185 , H01L23/3192 , H01L24/19 , H01L24/20 , H01L25/0655 , H01L25/072 , H01L21/561 , H01L2224/04105 , H01L2224/11 , H01L2224/12105 , H01L2224/16227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244
Abstract: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.
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公开(公告)号：US12068303B2
公开(公告)日：2024-08-20
申请号：US18481975
申请日：2023-10-05
Inventor： Wei-Hung Lin , Hui-Min Huang , Chang-Jung Hsueh , Wan-Yu Chiang , Ming-Da Cheng , Mirng-Ji Lii
IPC: H01L25/18 , H01L21/78 , H01L23/00 , H01L23/31 , H01L23/498
CPC classification number: H01L25/18 , H01L21/78 , H01L23/3107 , H01L23/49838 , H01L24/96
Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
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公开(公告)号：US11990440B2
公开(公告)日：2024-05-21
申请号：US17459174
申请日：2021-08-27
Inventor： Hui-Min Huang , Ming-Da Cheng , Wei-Hung Lin , Chang-Jung Hsueh , Kai-Jun Zhan , Yung-Sheng Lin
IPC: H01L23/00
CPC classification number: H01L24/14 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0221 , H01L2224/0401 , H01L2224/1147 , H01L2224/13018 , H01L2224/14051 , H01L2224/16227
Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.
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公开(公告)号：US11817413B2
公开(公告)日：2023-11-14
申请号：US17460647
申请日：2021-08-30
Inventor： Neng-Chieh Chang , Po-Hao Tsai , Ming-Da Cheng , Wen-Hsiung Lu , Hsu-Lun Liu
CPC classification number: H01L24/20 , H01L21/561 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/105 , H01L24/04 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05569 , H01L2224/13024 , H01L2224/19 , H01L2224/214 , H01L2224/215 , H01L2224/24175 , H01L2224/821 , H01L2225/1035 , H01L2225/1058 , H01L2924/01013 , H01L2924/01029
Abstract: A semiconductor package structure includes a conductive pad formed over a substrate. The structure also includes a passivation layer formed over the conductive pad. The structure also includes a first via structure formed through the passivation layer and in contact with the conductive pad. The structure also includes a first encapsulating material surrounding the first via structure. The structure also includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure.
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Patent Agency Ranking
公开(公告)号：US11776945B2
公开(公告)日：2023-10-03
申请号：US16580617
申请日：2019-09-24
Inventor： Meng-Tse Chen , Kuei-Wei Huang , Tsai-Tsung Tsai , Ai-Tee Ang , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L23/02 , H01L21/44 , H01L21/48 , H01L25/00 , H01L23/31 , H01L23/10 , H01L23/42 , H01L23/498 , H01L23/538 , H01L23/00 , H01L25/10 , H01L21/56
CPC classification number: H01L25/50 , H01L21/56 , H01L23/10 , H01L23/3128 , H01L23/42 , H01L23/49811 , H01L23/5385 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00012 , H01L2224/73265 , H01L2224/32145 , H01L2224/48227 , H01L2924/00012 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00
Abstract: A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.
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公开(公告)号：US20230068485A1
公开(公告)日：2023-03-02
申请号：US17461999
申请日：2021-08-31
Inventor： Chang-Jung Hsueh , Cheng-Nan Lin , Wan-Yu Chiang , Wei-Hung Lin , Ching-Wen Hsiao , Ming-Da Cheng
IPC: H01L23/31 , H01L23/522 , H01L23/498 , H01L23/00 , H01L21/78
Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.
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公开(公告)号：US20230065724A1
公开(公告)日：2023-03-02
申请号：US17459135
申请日：2021-08-27
Inventor： Ming-Da Cheng , Wei-Hung Lin , Hui-Min Huang , Chang-Jung Hsueh , Po-Hao Tsai , Yung-Sheng Lin
IPC: H01L23/522 , H01L23/00 , H01L21/48
Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate. The semiconductor device structure includes a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate. The semiconductor device structure includes an upper conductive via between the conductive pillar and the interconnection structure. A center of the upper conductive via is laterally separated from a center of the protruding portion by a first distance. The semiconductor device structure includes a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. A center of the lower conductive via is laterally separated from the center of the protruding portion by a second distance that is shorter than the first distance.
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公开(公告)号：US20210288012A1
公开(公告)日：2021-09-16
申请号：US17333754
申请日：2021-05-28
Inventor： Wei-Hung Lin , Hsiu-Jen Lin , Ming-Da Cheng , Yu-Min Liang , Chen-Shien Chen , Chung-Shi Liu
IPC: H01L23/00
Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
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公开(公告)号：US11121104B2
公开(公告)日：2021-09-14
申请号：US15878195
申请日：2018-01-23
Inventor： Meng-Tse Chen , Hsiu-Jen Lin , Chih-Wei Lin , Ming-Da Cheng , Chih-Hang Tung , Chung-Shi Liu
Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).
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