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公开(公告)号:US11962441B2
公开(公告)日:2024-04-16
申请号:US17814641
申请日:2022-07-25
发明人: Chaitanya Palusa , Rob Abbott , Wei-Li Chen , Po-Hsiang Lan , Dirk Pfaff , Cheng-Hsiang Hsieh
CPC分类号: H04L25/03878 , H03K5/135 , H04L25/028 , H04L25/03038 , H04L25/03057 , H04L27/01 , H03K2005/00052 , H03K2005/00065
摘要: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.
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公开(公告)号:US11240075B2
公开(公告)日:2022-02-01
申请号:US17157114
申请日:2021-01-25
发明人: Chaitanya Palusa , Rob Abbott , Rolando Ramirez , Wei-Li Chen , Dirk Pfaff , Cheng-Hsiang Hsieh , Fan-ming Kuo
摘要: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.
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公开(公告)号:US20210305131A1
公开(公告)日:2021-09-30
申请号:US17346186
申请日:2021-06-11
发明人: Yu-Hung Cheng , Shih-Pei Chou , Yeur-Luen Tu , Alexander Kalnitsky , Tung-I Lin , Wei-Li Chen
IPC分类号: H01L23/48 , H01L27/12 , H01L21/306 , H01L21/20 , H01L21/762 , H01L21/683 , H01L21/768
摘要: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.
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公开(公告)号:US10971406B2
公开(公告)日:2021-04-06
申请号:US16658597
申请日:2019-10-21
发明人: Yu-Hung Cheng , Ching-Wei Tsai , Yeur-Luen Tu , Tung-I Lin , Wei-Li Chen
IPC分类号: H01L29/267 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/66
摘要: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
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公开(公告)号:US20200252248A1
公开(公告)日:2020-08-06
申请号:US16741188
申请日:2020-01-13
发明人: Chaitanya Palusa , Rob Abbott , Rolando Ramirez , Wei-Li Chen , Dirk Pfaff , Cheng-Hsiang Hsieh , Fan-ming Kuo
摘要: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.
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公开(公告)号:US09978650B2
公开(公告)日:2018-05-22
申请号:US14581970
申请日:2015-01-06
发明人: Yu-Hung Cheng , Ching-Wei Tsai , Yeur-Luen Tu , Tung-I Lin , Wei-Li Chen
IPC分类号: H01L29/267 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/66
CPC分类号: H01L21/823821 , H01L27/0924 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要: A transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion, a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material.
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公开(公告)号:US20180047777A1
公开(公告)日:2018-02-15
申请号:US15790242
申请日:2017-10-23
发明人: Yu-Hung Cheng , Yeur-Luen Tu , Tung-I Lin , Cheng-Lung Wu , Wei-Li Chen
IPC分类号: H01L27/146
CPC分类号: H01L27/14683 , H01L27/1463 , H01L27/1464
摘要: Deep trench isolation (DTI) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate. A recess is formed in the substrate, the substrate comprising a first semiconductor material, the recess being interposed between adjacent photosensitive regions. The recess is enlarged by removing a damaged layer of the substrate along sidewalls of the recess, thereby forming an enlarged recess. An epitaxial region is formed on sidewalls and a bottom of the enlarged recess, at least a portion of the epitaxial region comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material. A dielectric region is formed on the epitaxial region, the epitaxial region extending along a sidewall of the dielectric region.
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公开(公告)号:US09887235B2
公开(公告)日:2018-02-06
申请号:US14967046
申请日:2015-12-11
发明人: Yu-Hung Cheng , Tung-I Lin , Wei-Li Chen , Yeur-Luen Tu
IPC分类号: H01L21/00 , H01L27/146
CPC分类号: H01L27/14689
摘要: Backside illuminated (BSI) image sensor devices are described as having pixel isolation structures formed on a sacrificial substrate. A photolayer is epitaxially grown over the pixel isolation structures. Radiation-detecting regions are formed in the photolayer adjacent to the pixel isolation structures. The pixel isolation structures include a dielectric material. The radiation-detecting regions include photodiodes. A backside surface of the BSI image sensor device is produced by planarized removal of the sacrificial substrate to physically expose the pixel isolation structures or at least optically expose the photolayer.
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公开(公告)号:US20170278893A1
公开(公告)日:2017-09-28
申请号:US15079781
申请日:2016-03-24
发明人: Yu-Hung Cheng , Yeur-Luen Tu , Tung-I Lin , Cheng-Lung Wu , Wei-Li Chen
IPC分类号: H01L27/146
CPC分类号: H01L27/14683 , H01L27/1463 , H01L27/1464
摘要: Deep trench isolation (DTI) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate. A recess is formed in the substrate, the substrate comprising a first semiconductor material, the recess being interposed between adjacent photosensitive regions. The recess is enlarged by removing a damaged layer of the substrate along sidewalls of the recess, thereby forming an enlarged recess. An epitaxial region is formed on sidewalls and a bottom of the enlarged recess, at least a portion of the epitaxial region comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material. A dielectric region is formed on the epitaxial region, the epitaxial region extending along a sidewall of the dielectric region.
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公开(公告)号:US09098757B2
公开(公告)日:2015-08-04
申请号:US13926596
申请日:2013-06-25
发明人: Tsung-Hsiung Lee , Kuang-Kai Yen , Shi-Hung Wang , Yung-Hsu Chuang , Huan-Neng Chen , Wei-Li Chen , Shih-Hung Lan , Yi-Hsuan Liu , Fan-Ming Kuo , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号: G01R31/26 , G06K7/00 , G01R31/265 , G01R31/302
CPC分类号: G06K7/0095 , G01R31/2656 , G01R31/3025
摘要: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.
摘要翻译: 半导体晶片包括多个管芯。 多个管芯中的每一个都包括射频识别(RFID)标签电路和线圈。 RFID标签电路包括标签芯,RF前端电路,ID解码器,用于唯一ID的比较器和导线。 RF前端电路被配置为通过多个管芯中的每一个中的线圈接收电磁信号,并将接收到的电磁信号转换为命令。 ID解码器被配置为接收命令并产生期望ID。 比较器被配置为将唯一ID与期望ID进行比较以产生比较结果。 布置比较结果来确定标签核心是否配置为接收命令。
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