-
公开(公告)号：US20200321969A1
公开(公告)日：2020-10-08
申请号：US16908786
申请日：2020-06-23
发明人： Jayawardan JANARDHANAN , Christopher Andrew SCHELL , Arvind SRIDHAR , Sinjeet Dhanvantray PAREKH
摘要： A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
-
公开(公告)号：US20190339651A1
公开(公告)日：2019-11-07
申请号：US16403774
申请日：2019-05-06
摘要： A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.
-
公开(公告)号：US20190288699A1
公开(公告)日：2019-09-19
申请号：US16227777
申请日：2018-12-20
发明人： Sinjeet Dhanvantray PAREKH , Jayawardan JANARDHANAN , Christopher Andrew SCHELL , Arvind SRIDHAR
摘要： A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.
-
公开(公告)号：US20200177192A1
公开(公告)日：2020-06-04
申请号：US16780957
申请日：2020-02-04
摘要： A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.
-
公开(公告)号：US20190288695A1
公开(公告)日：2019-09-19
申请号：US16233972
申请日：2018-12-27
摘要： A phase-locked loop (PLL) system includes a first PLL coupled to receive a first reference clock. The PLL system also includes a second PLL coupled to receive a second reference clock. The output of the second PLL is coupled to the first PLL, and the second PLL is configured to control the first PLL. The PLL system further includes a third PLL coupled to receive an input reference clock. The output of the third PLL is coupled to the second PLL. The third PLL is configured to control the second PLL.
-
公开(公告)号：US20190280700A1
公开(公告)日：2019-09-12
申请号：US16218970
申请日：2018-12-13
摘要： A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.
-
公开(公告)号：US20200021301A1
公开(公告)日：2020-01-16
申请号：US16582341
申请日：2019-09-25
发明人： Jayawardan JANARDHANAN , Christopher Andrew SCHELL , Arvind SRIDHAR , Sinjeet Dhanvantray PAREKH
摘要： A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
-
公开(公告)号：US20190339650A1
公开(公告)日：2019-11-07
申请号：US15991020
申请日：2018-05-29
摘要： A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.
-
9.发明申请公开(公告)号：US20190288694A1
公开(公告)日：2019-09-19
申请号：US16226938
申请日：2018-12-20
发明人： Sinjeet Dhanvantray PAREKH , Eric Paul LINDGREN , Christopher Andrew SCHELL , Jayawardan JANARDHANAN
摘要： A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.
-
公开(公告)号：US20190280699A1
公开(公告)日：2019-09-12
申请号：US16233283
申请日：2018-12-27
发明人： Jayawardan JANARDHANAN , Christopher Andrew SCHELL , Arvind SRIDHAR , Sinjeet Dhanvantray PAREKH
摘要： A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.013 秒)