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    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
    3.
    发明申请
    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW 有权
    在门电路第一流程中生长应变诱导材料的方法

    公开(公告)号：US20120104507A1

    公开(公告)日：2012-05-03

    申请号：US12938457

    申请日：2010-11-03

    申请人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    发明人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823828

    摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.

    摘要翻译： 一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于 厚度减小 在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

    Method for growing strain-inducing materials in CMOS circuits in a gate first flow
    4.
    发明授权
    Method for growing strain-inducing materials in CMOS circuits in a gate first flow 有权
    在栅极第一流中在CMOS电路中增长应变诱导材料的方法

    公开(公告)号：US08426265B2

    公开(公告)日：2013-04-23

    申请号：US12938457

    申请日：2010-11-03

    申请人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    发明人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823828

    摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.

    摘要翻译： 一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于 厚度减小 在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

    MOS DEVICES WITH MULTI-LAYER GATE STACK
    7.
    发明申请
    MOS DEVICES WITH MULTI-LAYER GATE STACK 有权
    具有多层栅极堆叠的MOS器件

    公开(公告)号：US20090115001A1

    公开(公告)日：2009-05-07

    申请号：US12347061

    申请日：2008-12-31

    申请人： Chun-Li Liu ,  Marius K. Orlowski ,  Matthew W. Stoker

    发明人： Chun-Li Liu ,  Marius K. Orlowski ,  Matthew W. Stoker

    IPC分类号： H01L29/78

    CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

    摘要： An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.

    摘要翻译： 半导体器件的实施例包括半导体衬底，其具有主表面，间隔开的源极和漏极区域，其在主表面处由沟道区域分隔开，并且多层栅极结构位于沟道区域上方。 多层栅极结构包括与沟道区接触的栅极电介质层，包括覆盖栅极电介质层的金属氧化物的第一导体，覆盖第一导体的第二导体以及在栅极介电层和第二导体之间的杂质迁移抑制层 第一导体或第一导体与第二导体之间。

    TRANSISTOR DEVICES WITH NANO-CRYSTAL GATE STRUCTURES
    8.
    发明申请
    TRANSISTOR DEVICES WITH NANO-CRYSTAL GATE STRUCTURES 有权
    具有纳米晶体结构的晶体管器件

    公开(公告)号：US20100155825A1

    公开(公告)日：2010-06-24

    申请号：US12715947

    申请日：2010-03-02

    申请人： Chun-Li Liu ,  Tushar P. Merchant ,  Marius K. Orlowski ,  Matthew W. Stoker

    发明人： Chun-Li Liu ,  Tushar P. Merchant ,  Marius K. Orlowski ,  Matthew W. Stoker

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7883 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/78

    摘要： Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.

    摘要翻译： 非易失性半导体器件的实施例包括其中具有源极区域和漏极区域的衬底，所述源极区域和漏极区域被延伸到衬底的第一表面的沟道区域分开，以及包含位于沟道区域上方的纳米晶体的多层栅极结构。 栅极结构包括基本上与沟道区接触的栅极电介质，设置在栅极电介质中的间隔开的纳米晶体，覆盖栅极电介质的一个或多个杂质阻挡层，以及叠加在一个以上杂质阻挡层上的栅极导体层 。 可以使用最靠近栅极导体的阻挡层来调节器件的阈值电压和/或从栅极导体层延迟掺杂剂的扩散。

    MOS device with multi-layer gate stack
    9.
    发明授权
    MOS device with multi-layer gate stack 有权
    具有多层栅极堆叠的MOS器件

    公开(公告)号：US07510956B2

    公开(公告)日：2009-03-31

    申请号：US11343623

    申请日：2006-01-30

    申请人： Chun-Li Liu ,  Marius K. Orlowski ,  Matthew W. Stoker

    发明人： Chun-Li Liu ,  Marius K. Orlowski ,  Matthew W. Stoker

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

    摘要： Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.

    摘要翻译： 为半导体器件提供了方法和装置。 该装置包括其中具有源极区和漏极区的衬底，漏极区被延伸到衬底的第一表面的沟道区分离，以及位于沟道区上方的多层栅极结构。 栅极结构包括：栅极电介质，优选地与沟道区基本上接触的Hf，Zr或HfZr的氧化物，例如覆盖栅极电介质的MoSi的氧化物的第一导体层， 例如多晶硅，覆盖在第一导体层上并且适于向沟道区施加电场，以及位于第一导体层上方或下方的杂质迁移抑制层（例如MoSi），并适于抑制移动 杂质，例如氧气，朝向衬底。

    Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration
    10.
    发明授权
    Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration 有权
    采用具有渐变杂质浓度的应力诱导源极漏极结构的半导体制造工艺

    公开(公告)号：US07238580B2

    公开(公告)日：2007-07-03

    申请号：US11043577

    申请日：2005-01-26

    申请人： Marius K. Orlowski ,  Vance H. Adams ,  Chun-Li Liu ,  Matthew W. Stoker

    发明人： Marius K. Orlowski ,  Vance H. Adams ,  Chun-Li Liu ,  Matthew W. Stoker

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/28061 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

    摘要： A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.

    摘要翻译： 半导体制造工艺具有使用多相形成工艺形成的凹陷的应力诱导源极/漏极（SISD）结构。 SISD结构是具有不同于源/漏结构凹陷的半导体衬底的晶格常数的晶格常数的半导体结构。 SISD结构优选包括具有第一元素（例如硅）和第二元素（例如锗或碳）的半导体化合物。 SISD结构具有组成梯度，其中第二元素的百分比从源极/漏极结构的上表面到SISD结构的下表面变化。 SISD结构可以包括具有半导体化合物的第一组成的第一层，位于第二层下面，半导体化合物的第二组成。 第二层可以包括杂质，并且具有比第一层更高百分比的第二元素。