公开(公告)号：US20050083623A1

公开(公告)日：2005-04-21

申请号：US10964392

申请日：2004-10-13

申请人： Ta-Hsun Yeh ,  Yung-Hao Lin ,  Yuh-Sheng Jean

发明人： Ta-Hsun Yeh ,  Yung-Hao Lin ,  Yuh-Sheng Jean

IPC分类号： H01L29/70 ,  H01L21/33 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H02H9/00

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit for hybrid voltage sources includes a first bipolar transistor set and a second bipolar transistor set, a first detection circuit, and a second detection circuit. The ON/OFF states of the first bipolar transistor set and the second bipolar transistor set are determined by the first and the second detection circuit, and the ON/OFF states function to isolate terminals of the different voltage sources and discharge electrostatic charges injected into one of the terminals.

摘要翻译： 用于混合电压源的ESD保护电路包括第一双极晶体管组和第二双极晶体管组，第一检测电路和第二检测电路。 第一双极晶体管组和第二双极晶体管组的ON / OFF状态由第一和第二检测电路确定，并且ON / OFF状态用于隔离不同电压源的端子和将静电电荷注入一个 的终端。

公开(公告)号：US07245467B2

公开(公告)日：2007-07-17

申请号：US10964392

申请日：2004-10-13

申请人： Ta-Hsun Yeh ,  Yung-Hao Lin ,  Yuh-Sheng Jean

发明人： Ta-Hsun Yeh ,  Yung-Hao Lin ,  Yuh-Sheng Jean

IPC分类号： H02H9/00

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit for hybrid voltage sources includes a first bipolar transistor set and a second bipolar transistor set, a first detection circuit, and a second detection circuit. The ON/OFF states of the first bipolar transistor set and the second bipolar transistor set are determined by the first and the second detection circuit, and the ON/OFF states function to isolate terminals of the different voltage sources and discharge electrostatic charges injected into one of the terminals.

摘要翻译： 用于混合电压源的ESD保护电路包括第一双极晶体管组和第二双极晶体管组，第一检测电路和第二检测电路。 第一双极晶体管组和第二双极晶体管组的ON / OFF状态由第一和第二检测电路确定，并且ON / OFF状态用于隔离不同电压源的端子和将静电电荷注入一个 的终端。

公开(公告)号：US20050083620A1

公开(公告)日：2005-04-21

申请号：US10710093

申请日：2004-06-18

申请人： Yung-Hao Lin ,  Tay-Her Tsaur ,  Ta-Hsun Yeh ,  Chao-Cheng Lee

发明人： Yung-Hao Lin ,  Tay-Her Tsaur ,  Ta-Hsun Yeh ,  Chao-Cheng Lee

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H01L27/06 ,  H02H9/00

CPC分类号： H01L27/0266

摘要： An ESD protection circuit installed among a plurality of reference nodes includes a clamping device coupled between two reference nodes among the plurality of reference nodes; a stack-coupling device coupled between the clamping device and one of the reference nodes; and at least a resistive device coupled between the stack-coupling device and another one of the reference nodes.

摘要翻译： 安装在多个参考节点之间的ESD保护电路包括耦合在多个参考节点中的两个参考节点之间的夹紧装置; 耦合在所述夹持装置和所述参考节点之一之间的叠层耦合装置; 以及耦合在所述堆叠耦合装置与所述参考节点中的另一个之间的至少一个电阻装置。

公开(公告)号：US07279931B2

公开(公告)日：2007-10-09

申请号：US11162001

申请日：2005-08-25

申请人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

发明人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

IPC分类号： H03K19/0175

CPC分类号： H01L27/0928 ,  H03K17/102

摘要： An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

摘要翻译： 输出级结构包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管，其中MOS晶体管是用双阱工艺制造的。 第一PMOS晶体管具有耦合到电源电压（VDD）的源极和耦合到第一电压的栅极。 第二PMOS晶体管具有耦合到第一PMOS晶体管的漏极的源极，耦合到第二电压的栅极和耦合到输出焊盘的漏极。 第一NMOS晶体管具有耦合到输出焊盘的漏极和耦合到第三电压的栅极。 第二NMOS晶体管具有耦合到第一NMOS晶体管的源极的漏极，耦合到第四电压的栅极和耦合到地的源极。

公开(公告)号：US20060044015A1

公开(公告)日：2006-03-02

申请号：US11162001

申请日：2005-08-25

申请人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

发明人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

IPC分类号： H03K19/0175

CPC分类号： H01L27/0928 ,  H03K17/102

摘要： An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

摘要翻译： 输出级结构包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管，其中MOS晶体管是用双阱工艺制造的。 第一PMOS晶体管具有耦合到电源电压（VDD）的源极和耦合到第一电压的栅极。 第二PMOS晶体管具有耦合到第一PMOS晶体管的漏极的源极，耦合到第二电压的栅极和耦合到输出焊盘的漏极。 第一NMOS晶体管具有耦合到输出焊盘的漏极和耦合到第三电压的栅极。 第二NMOS晶体管具有耦合到第一NMOS晶体管的源极的漏极，耦合到第四电压的栅极和耦合到地的源极。

公开(公告)号：US5567638A

公开(公告)日：1996-10-22

申请号：US490401

申请日：1995-06-14

申请人： Yung-Hao Lin ,  Chao-Sung Lai ,  Chung-Len Lee ,  Tan-Fu Lei

发明人： Yung-Hao Lin ,  Chao-Sung Lai ,  Chung-Len Lee ,  Tan-Fu Lei

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/265

CPC分类号： H01L29/4916 ,  H01L21/28035 ,  H01L21/28061 ,  H01L29/4925

摘要： A method for suppressing boron penetration in a PMOS with a nitridized polysilicon gate includes steps of 1) growing a layer of gate oxide on a substrate, 2) forming at least one first polysilicon layer on the gate oxide layer, 3) nitridizing the first polysilicon layer, 4) forming a second polysilicon layer on the first polysilicon layer; and 5) implanting B-containing ions into the first and second polysilicon layers for constructing a PMOS structure wherein the nitridizing step suppresses a boron ion from penetration into the substrate. The present invention is characterized in nitridation on a polysilicon gate instead of a gate oxide which can effectively suppress boron penetration, avoid drawbacks resulting from nitridizing a gate oxide, and moreover, improve the reliability of the device owing to the slight nitridation effect in the polysilicon gate and the gate oxide.

摘要翻译： 一种抑制具有氮化多晶硅栅极的PMOS中的硼渗透的方法包括以下步骤：1）在衬底上生长栅极氧化层，2）在栅极氧化物层上形成至少一个第一多晶硅层，3）使第一多晶硅氮化 4）在第一多晶硅层上形成第二多晶硅层; 以及5）将含B离子注入到第一和第二多晶硅层中以构成PMOS结构，其中氮化步骤抑制硼离子渗透到基底中。 本发明的特征在于在多晶硅栅极上进行氮化，而不是可以有效抑制硼渗透的栅极氧化物，避免由于氮化栅极氧化物而导致的缺陷，而且由于多晶硅中的轻微的氮化作用，提高了器件的可靠性 栅极和栅极氧化物。