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    DUAL TURBO CENTRIFUGAL CHILLER
    1.
    发明申请
    DUAL TURBO CENTRIFUGAL CHILLER 审中-公开
    双涡轮离心机

    公开(公告)号：US20110094251A1

    公开(公告)日：2011-04-28

    申请号：US12796014

    申请日：2010-06-08

    Applicant: Kil Young Kim ,  Jin Sung Kim ,  Tae Jin Kang

    Inventor： Kil Young Kim ,  Jin Sung Kim ,  Tae Jin Kang

    IPC: F25B7/00 ,  F25B1/10

    CPC classification number: F25B1/053 ,  F25B1/10 ,  F25B2339/047 ,  F25B2400/0751

    Abstract: A dual turbo centrifugal chiller includes: first and second evaporators connected in series or in parallel; first and second condensers connected in series or in parallel; and first and second compressors including impellers, wherein cold water passes through the second evaporator after passing through the first evaporator, and cooling water passes through the second condenser after passing through the first condenser, the first compressor containing a refrigerant connects the first condenser to the second evaporator, and the second compressor containing a refrigerant connects the second condenser to the first evaporator, and the impellers of the first compressor and second compressor are rotated simultaneously using a single driving unit.

    Abstract translation: 双涡轮离心式冷冻机包括：串联或并联连接的第一和第二蒸发器; 串联或并联连接的第一和第二电容器; 以及包括叶轮的第一和第二压缩机，其中冷水在通过第一蒸发器之后通过第二蒸发器，并且冷却水在通过第一冷凝器之后通过第二冷凝器，含有制冷剂的第一压缩机将第一冷凝器连接到 第二蒸发器，并且包含制冷剂的第二压缩机将第二冷凝器连接到第一蒸发器，并且使用单个驱动单元同时旋转第一压缩机和第二压缩机的叶轮。

    Level shifter with reduced current consumption
    2.
    发明申请
    Level shifter with reduced current consumption 失效
    电平移位器，降低电流消耗

    公开(公告)号：US20090237139A1

    公开(公告)日：2009-09-24

    申请号：US12215774

    申请日：2008-06-30

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: H03L5/00

    CPC classification number: H03K3/35613 ,  H03K3/012

    Abstract: A level shifter includes a level shifting unit for level-shifting an input signal at a first voltage level into a signal at a second voltage level, and an output controller for controlling the level shifting unit to maintain output at a predetermined logic level in response to a deep power down mode signal generated from power which is not turned off in a deep power down mode.

    Abstract translation: 电平移位器包括电平移位单元，用于将处于第一电压电平的输入信号电平转换为第二电压电平的信号;以及输出控制器，用于控制电平移位单元，以响应于电平移位单元将输出维持在预定逻辑电平 在深度掉电模式下从未关闭的电源产生的深度掉电模式信号。

    Control signal generation circuits, semiconductor modules, and semiconductor systems including the same
    4.
    发明授权
    Control signal generation circuits, semiconductor modules, and semiconductor systems including the same 有权
    控制信号发生电路，半导体模块和包括它们的半导体系统

    公开(公告)号：US08610460B2

    公开(公告)日：2013-12-17

    申请号：US13590885

    申请日：2012-08-21

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: H03K17/16 ,  H03K19/003 ,  G11C5/14 ,  G11C7/10

    CPC classification number: G11C7/1045 ,  G11C7/1057 ,  G11C7/1084

    Abstract: Semiconductor modules are provided. The semiconductor module includes a first semiconductor chip configured for storing an information signal that is set in response to a command/address signal and which determines reception of an on-die termination (ODT) signal in a power down mode in response to the information signal to control activation of a first ODT circuit; and a second semiconductor chip configured for sharing and utilizing the first ODT circuit included in the first semiconductor chip.

    Abstract translation: 提供半导体模块。 半导体模块包括：第一半导体芯片，被配置为存储响应于命令/地址信号设置的信息信号，并且响应于信息信号确定在断电模式下接收片上终端（ODT）信号 以控制第一ODT电路的激活; 以及配置为共享和利用包括在第一半导体芯片中的第一ODT电路的第二半导体芯片。

    Clock enable buffer for entry of self-refresh mode
    6.
    发明授权
    Clock enable buffer for entry of self-refresh mode 有权
    用于进入自刷新模式的时钟使能缓冲区

    公开(公告)号：US07142022B2

    公开(公告)日：2006-11-28

    申请号：US10739232

    申请日：2003-12-18

    Applicant: Tae Jin Kang ,  Kee Teok Park

    Inventor： Tae Jin Kang ,  Kee Teok Park

    IPC: G01R19/00

    CPC classification number: G11C7/225 ,  G11C7/22 ,  H03K5/2481 ,  H03K19/0016 ,  H03K19/018528

    Abstract: A clock enable buffer for entry of a self-refresh mode. The clock enable buffer includes a current mirror load connected between a voltage source and first and second nodes, wherein the current mirror load has first and second transistors; a third transistor connected between the first node and a third node, wherein the third transistor is turned on according to a reference voltage; a fourth transistor connected between the second node and the third node, for controlling the current mirror load in response to a clock enable signal; a fifth transistor connected between the third node and a ground, wherein the fifth transistor is turned on according to a self-refresh signal; and a sixth transistor that is turned on according to an inverted self-refresh signal to make the potential of the first node a Low level.

    Abstract translation: 用于输入自刷新模式的时钟使能缓冲器。 所述时钟使能缓冲器包括连接在电压源和第一和第二节点之间的电流镜像负载，其中电流反射镜负载具有第一和第二晶体管; 连接在所述第一节点和第三节点之间的第三晶体管，其中所述第三晶体管根据参考电压导通; 连接在第二节点和第三节点之间的第四晶体管，用于响应于时钟使能信号控制电流镜像负载; 连接在所述第三节点和地之间的第五晶体管，其中所述第五晶体管根据自刷新信号导通; 以及根据反相自刷新信号导通的第六晶体管，以使第一节点的电位为低电平。

    Semiconductor modules
    7.
    发明授权
    Semiconductor modules 有权
    半导体模块

    公开(公告)号：US08896340B2

    公开(公告)日：2014-11-25

    申请号：US13615373

    申请日：2012-09-13

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: H03K19/003

    CPC classification number: H03K19/0005

    Abstract: Semiconductor modules are provided. The semiconductor module includes semiconductor chips with one or more ranks. The semiconductor module includes a mode register configured for storing a first information signal whose logic level is set or determined according to a number of the ranks and an on-die termination (ODT) controller configured for generating an internal control signal for activating an ODT circuit in response to the first information signal. The internal control signal is enabled during a read operation or disabled during a write operation.

    Abstract translation: 提供半导体模块。 半导体模块包括具有一个或多个等级的半导体芯片。 半导体模块包括模式寄存器，其被配置为存储根据等级的数量来设置或确定其逻辑电平的第一信息信号，以及配置用于生成用于激活ODT电路的内部控制信号的片上终端（ODT）控制器 响应于第一信息信号。 内部控制信号在读操作期间被使能，或者在写操作期间被禁止。

    Semiconductor memory device and semiconductor system
    8.
    发明授权
    Semiconductor memory device and semiconductor system 有权
    半导体存储器件和半导体系统

    公开(公告)号：US08699279B2

    公开(公告)日：2014-04-15

    申请号：US13336876

    申请日：2011-12-23

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: G11C7/10

    CPC classification number: G11C29/56008 ,  G11C29/56012

    Abstract: A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the read command, in synchronization with a pulse generated when a level of the information data changes.

    Abstract translation: 半导体系统包括：半导体存储器件，被配置为在测试模式期间响应于写入命令将接收到的数据存储在存储器单元中，响应于读取命令读取存储的数据作为信息数据，并在内部存储信息数据 响应于读取命令，与信息数据的级别变化时产生的脉冲同步。

    Electrically conductive metal composite embroidery yarn and embroidered circuit using thereof
    9.
    发明授权
    Electrically conductive metal composite embroidery yarn and embroidered circuit using thereof 有权
    导电金属复合绣花线及其使用的绣花线路

    公开(公告)号：US08505474B2

    公开(公告)日：2013-08-13

    申请号：US12668930

    申请日：2008-07-30

    Applicant: Tae Jin Kang ,  Byung Duck Kim ,  Young Seung Chi ,  Jung Sim Roh

    Inventor： Tae Jin Kang ,  Byung Duck Kim ,  Young Seung Chi ,  Jung Sim Roh

    IPC: D05B3/00 ,  D02G3/36

    CPC classification number: D02G3/12 ,  A41D27/00 ,  D02G3/28 ,  D02G3/441 ,  D05C7/06 ,  D10B2331/04 ,  H05K1/038 ,  H05K2201/0281 ,  H05K2201/029

    Abstract: The present invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit using thereof which may be applicable to smart textiles. More particularly, this invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit for smart textiles which can be used as power supply and signal transmission lines. The present invention provides an embroidered circuit which consists of a metal composite embroidery yarn and a dielectric fabric substrate, wherein the electrically conductive metal composite embroidery yarn is embroidered on the dielectric fabric substrate to form a circuit.

    Abstract translation: 本发明涉及可应用于智能纺织品的导电金属复合刺绣线及其使用的绣花电路。 更具体地，本发明涉及可用作电源和信号传输线的智能纺织品的导电金属复合刺绣线和绣花电路。 本发明提供了一种由金属复合刺绣纱线和电介质织物基材组成的绣花线路，其中将导电金属复合刺绣纱线绣在电介质织物基底上以形成电路。

    Power control circuit and semiconductor memory device using the same
    10.
    发明授权
    Power control circuit and semiconductor memory device using the same 有权
    功率控制电路和使用其的半导体存储器件

    公开(公告)号：US08054709B2

    公开(公告)日：2011-11-08

    申请号：US12459345

    申请日：2009-06-30

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: G11C5/14

    CPC classification number: G11C5/147 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

    Abstract: A semiconductor memory device comprises a power control circuit for outputting a power voltage in a read operation period and a write operation period, and an internal circuit operating by the power voltage supplied thereto.

    Abstract translation: 半导体存储器件包括用于在读操作期间和写操作期间输出电源电压的电源控制电路，以及由供给的电源电压进行工作的内部电路。

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