公开(公告)号：US20080128786A1

公开(公告)日：2008-06-05

申请号：US11950291

申请日：2007-12-04

申请人： Taeyoub KIM ,  Myungsim JUN ,  Yark-Yeon KIM ,  Moon-Gyu JANG ,  Chel-Jong CHOI ,  Seong-Jae LEE ,  Byoungchul PARK

发明人： Taeyoub KIM ,  Myungsim JUN ,  Yark-Yeon KIM ,  Moon-Gyu JANG ,  Chel-Jong CHOI ,  Seong-Jae LEE ,  Byoungchul PARK

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/788 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/41725 ,  H01L29/42324 ,  H01L29/47 ,  H01L29/66825 ,  H01L29/7839 ,  H01L29/78654 ,  H01L29/7881

摘要： Provided are a high density semiconductor memory device capable of precisely reading data by suppressing the occurrence of a leakage current due to the high-integration of the semiconductor memory device, and a method for manufacturing the semiconductor memory device. The high density semiconductor memory device includes: source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots. The nanodots may be formed of a silicon compound or any material that can be charged.

摘要翻译： 提供一种能够通过抑制由于半导体存储器件的高集成度而导致的漏电流的发生而精确读取数据的高密度半导体存储器件以及半导体存储器件的制造方法。 高密度半导体存储器件包括：源极和漏极，设置在衬底上，并与沟道区形成肖特基结; 以及浮置栅极，设置在沟道区域的衬底上，并且配置有多个纳米点。 纳米点可以由硅化合物或可以被充电的任何材料形成。

公开(公告)号：US20080124854A1

公开(公告)日：2008-05-29

申请号：US11744927

申请日：2007-05-07

申请人： Chel-Jong CHOI ,  Moon-Gyu JANG ,  Yark-Yeon KIM ,  Tae-Youb KIM ,  Myung-Sim JUN ,  Seong-Jae LEE

发明人： Chel-Jong CHOI ,  Moon-Gyu JANG ,  Yark-Yeon KIM ,  Tae-Youb KIM ,  Myung-Sim JUN ,  Seong-Jae LEE

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/78

摘要： A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a conductive compound containing layer over the gate insulation layer, etching the conductive compound containing layer and the gate insulation layer to form a gate structure, forming a metal layer over the resultant structure obtained after the etching, and letting the metal layer to react with silicon from the substrate to form source and drain regions comprising a metal silicide layer over the substrate exposed on both sides of the gate structure, wherein the conductive compound containing layer does not react with the metal layer.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成栅极绝缘层，在栅极绝缘层上形成导电化合物含有层，蚀刻导电化合物层和栅极绝缘层以形成栅极结构，形成金属层 在蚀刻之后获得的结果结构上，并且使金属层与来自衬底的硅反应以形成在暴露于栅极结构的两侧的衬底上的包含金属硅化物层的源区和漏区，其中导电化合物含有层 不与金属层反应。