公开(公告)号：US20050048747A1

公开(公告)日：2005-03-03

申请号：US10964875

申请日：2004-10-13

申请人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara Kurdoghlian

发明人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara Kurdoghlian

IPC分类号： H01L21/24 ,  H01L21/285 ,  H01L21/335 ,  H01L21/337 ,  H01L29/20 ,  H01L29/45 ,  H01L21/28

CPC分类号： H01L29/66462 ,  H01L21/24 ,  H01L21/242 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66924

摘要： A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

公开(公告)号：US06884704B2

公开(公告)日：2005-04-26

申请号：US10634348

申请日：2003-08-04

申请人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

发明人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

IPC分类号： H01L21/24 ,  H01L21/285 ,  H01L21/335 ,  H01L21/337 ,  H01L29/20 ,  H01L29/45 ,  H01L21/48 ,  H01L21/38

CPC分类号： H01L29/66462 ,  H01L21/24 ,  H01L21/242 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66924

摘要： A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

摘要翻译： 说明了在随后的高温处理步骤中制造保护欧姆金属触点和器件通道的半导体器件的方法。 封装层用于覆盖通道和欧姆金属触点。 本发明提供一种其上沉积有多个半导体层的衬底。 半导体层用作器件的通道。 半导体层被封装层覆盖。 去除封装层和多个半导体层的一部分，其中沉积欧姆金属接触。 然后将欧姆金属触点退火以帮助降低其电阻。 封装层确保在退火步骤期间欧姆金属触点不迁移，并且该通道不会受退火步骤期间所需的高温的损害。

公开(公告)号：US08030688B2

公开(公告)日：2011-10-04

申请号：US12486686

申请日：2009-06-17

申请人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

发明人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

IPC分类号： H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/24 ,  H01L21/242 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66924

摘要： A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

摘要翻译： 说明了在随后的高温处理步骤中制造保护欧姆金属触点和器件通道的半导体器件的方法。 封装层用于覆盖通道和欧姆金属触点。 本发明提供一种其上沉积有多个半导体层的衬底。 半导体层用作器件的通道。 半导体层被封装层覆盖。 去除封装层和多个半导体层的一部分，其中沉积欧姆金属接触。 然后将欧姆金属触点退火以帮助降低它们的电阻。 封装层确保在退火步骤期间欧姆金属接触不迁移，并且该通道不会受退火步骤期间所需的高温的损害。

公开(公告)号：US07566916B2

公开(公告)日：2009-07-28

申请号：US10964875

申请日：2004-10-13

申请人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

发明人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

IPC分类号： H01L31/072

CPC分类号： H01L29/66462 ,  H01L21/24 ,  H01L21/242 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66924

摘要： A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

摘要翻译： 说明了在随后的高温处理步骤中制造保护欧姆金属触点和器件通道的半导体器件的方法。 封装层用于覆盖通道和欧姆金属触点。 本发明提供一种其上沉积有多个半导体层的衬底。 半导体层用作器件的通道。 半导体层被封装层覆盖。 去除封装层和多个半导体层的一部分，其中沉积欧姆金属接触。 然后将欧姆金属触点退火以帮助降低其电阻。 封装层确保在退火步骤期间欧姆金属接触不迁移，并且该通道不会受退火步骤期间所需的高温的损害。

公开(公告)号：US06852615B2

公开(公告)日：2005-02-08

申请号：US10457506

申请日：2003-06-09

申请人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Janna Ruth Duvall

发明人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Janna Ruth Duvall

IPC分类号： H01L21/285 ,  H01L29/20 ,  H01L29/417 ,  H01L29/45 ,  H10L21/338

CPC分类号： H01L29/452 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/41725 ,  Y10S438/975 ,  Y10S438/978

摘要： A process and related product in which ohmic contacts are formed in High Electron Mobility Transistors (HEMTs) employing compound substrates such as gallium nitride. An improved device and an improvement to a process for fabrication of ohmic contacts to GaN/AlGaN HEMTs using a novel two step resist process to fabricate the ohmic contacts are described. This novel two-step process consists of depositing a plurality of layers having compounds of Group III V elements on a substrate; patterning and depositing a first photoresist on one of the layers; etching recessed areas into this layer; depositing ohmic metals on the recessed areas; removing the first photoresist; patterning and depositing a second photoresist, smaller in profile than the first photoresist, on the layer; depositing more ohmic metal on the layer allowing for complete coverage of the recessed areas; removing the second photoresist, and annealing the semiconductor structure.

摘要翻译： 在使用诸如氮化镓的复合衬底的高电子迁移率晶体管（HEMT）中形成欧姆接触的工艺及相关产品。 描述了使用新颖的两步抗蚀剂工艺制造欧姆接触的改进的器件和用于制造对GaN / AlGaN HEMT的欧姆接触的工艺的改进。 这种新型的两步法包括在基片上沉积多层具有IIIV族元素化合物的层; 在其中一层上图案化和沉积第一光致抗蚀剂; 将凹陷区域蚀刻到该层中; 在凹陷区域沉积欧姆金属; 去除第一光致抗蚀剂; 在该层上图案化和沉积比第一光致抗蚀剂更小的第二光致抗蚀剂; 在该层上沉积更多的欧姆金属，允许完全覆盖凹陷区域; 去除第二光致抗蚀剂，并退火半导体结构。

公开(公告)号：US07470941B2

公开(公告)日：2008-12-30

申请号：US10313374

申请日：2002-12-06

申请人： Miroslav Micovic ,  Mike Antcliffe ,  Tahir Hussain ,  Paul Hashimoto

发明人： Miroslav Micovic ,  Mike Antcliffe ,  Tahir Hussain ,  Paul Hashimoto

IPC分类号： H01L31/0328

CPC分类号： H01L29/66462 ,  H01L21/28575 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/7787

摘要： A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

摘要翻译： 提出了一种用于制造异质结场效应晶体管（HFET）和一系列HFET层结构的方法。 在该方法中，执行将HFET半导体结构沉积到衬底上的步骤。 接下来，沉积光致抗蚀剂材料。 对应于源极和漏极焊盘对，去除部分光致抗蚀剂材料。 金属层沉积在结构上，形成源极焊盘和漏极焊盘对。 去除光致抗蚀剂材料，将其暴露于不同于源极和漏极焊盘对的区域中。 每个源极和漏极焊盘对具有相应的曝光区域。 该结构进行退火，并且器件是电隔离的。 蚀刻每个器件的暴露面积以形成栅极凹部，并且在凹部中形成栅极结构。 还提出了用于GaN / AlGaN HFET的半导体层结构。

公开(公告)号：US07098490B2

公开(公告)日：2006-08-29

申请号：US10832691

申请日：2004-04-26

申请人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Peter W. Deelman

发明人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Peter W. Deelman

IPC分类号： H01L29/772

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/7787

摘要： The present invention provides a GaN based DHFET that helps confine the 2DEG to the channel layer, and reduces the 2DHG. The present invention provides a GaN DHFET having a channel layer comprising GaN and a buffer layer comprising AlxGa1−xN. The Al content in the buffer layer is specifically chosen based on the thickness of the channel layer using a graph. By choosing the Al content in the buffer layer and thickness of the channel layer in accordance with the graph provided in the present invention, the ability of the buffer layer to help confine the 2DEG to the channel layer is improved.

摘要翻译： 本发明提供了一种GaN基DHFET，其帮助将2DEG限制到沟道层，并且减少2DHG。 本发明提供了具有包含GaN的沟道层和包括Al x Ga 1-x N的缓冲层的GaN DHFET。 缓冲层中的Al含量是使用图表基于沟道层的厚度特别选择的。 通过根据本发明提供的图来选择缓冲层中的Al含量和沟道层的厚度，缓冲层有助于将2DEG限制到沟道层的能力得到改善。

公开(公告)号：US07598131B1

公开(公告)日：2009-10-06

申请号：US12290921

申请日：2008-11-05

申请人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Mike Antcliffe

发明人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Mike Antcliffe

IPC分类号： H01L21/338

CPC分类号： H01L29/66462 ,  H01L21/28575 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/7787

摘要： A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

摘要翻译： 提出了一种用于制造异质结场效应晶体管（HFET）和一系列HFET层结构的方法。 在该方法中，执行将HFET半导体结构沉积到衬底上的步骤。 接下来，沉积光致抗蚀剂材料。 对应于源极和漏极焊盘对，去除部分光致抗蚀剂材料。 金属层沉积在结构上，形成源极焊盘和漏极焊盘对。 去除光致抗蚀剂材料，将其暴露于不同于源极和漏极焊盘对的区域中。 每个源极和漏极焊盘对具有相应的曝光区域。 该结构进行退火，并且器件是电隔离的。 蚀刻每个器件的暴露面积以形成栅极凹部，并且在凹部中形成栅极结构。 还提出了用于GaN / AlGaN HFET的半导体层结构。

公开(公告)号：US08728884B1

公开(公告)日：2014-05-20

申请号：US12510687

申请日：2009-07-28

申请人： Tahir Hussain ,  Miroslav Micovic ,  Wah S. Wong ,  Shawn D. Burnham

发明人： Tahir Hussain ,  Miroslav Micovic ,  Wah S. Wong ,  Shawn D. Burnham

IPC分类号： H01L21/338

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462

摘要： A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.

摘要翻译： 一种制造具有源极和漏极的正常“关闭”GaN异质结构场效应晶体管的方法，包括沉积图案化以覆盖源极和漏极之间的沟道区域的钝化层，在钝化层中形成第一开口，第一开口 用于在所述沟道区域中限定栅极区域，并且所述第一开口沿着所述源极和漏极之间的电流流动的方向具有第一长度尺寸，以及将离子注入所述栅极区域内的注入区域中，其中所述植入区域具有第二 沿着电流流动方向的长度尺寸短于第一长度尺寸。

公开(公告)号：US08178946B1

公开(公告)日：2012-05-15

申请号：US12623325

申请日：2009-11-20

申请人： James Chingwei Li ,  Marko Sokolich ,  Tahir Hussain ,  David H. Chow

发明人： James Chingwei Li ,  Marko Sokolich ,  Tahir Hussain ,  David H. Chow

IPC分类号： H01L29/00

CPC分类号： H01L29/155 ,  H01L29/201 ,  H01L29/7373

摘要： A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.

摘要翻译： 具有发射极，基极和集电极的异质结双极晶体管（HBT），所述基极包括耦合到集电极的第一半导体层，所述第一半导体层在第一导带和第一价带之间具有第一带隙， 第二半导体层，其耦合到所述第一半导体层，并且在第二导带和第二价带之间具有第二带隙，其中所述第二价带高于所述第一价带，并且其中所述第二半导体层包括二维空穴气体， 耦合到所述第二半导体层并且在第三导带和第三价带之间具有第三带隙的第三半导体层，其中所述第三价带低于所述第二价带，并且其中所述第三半导体层耦合到所述发射极。