公开(公告)号：US08728884B1

公开(公告)日：2014-05-20

申请号：US12510687

申请日：2009-07-28

申请人： Tahir Hussain ,  Miroslav Micovic ,  Wah S. Wong ,  Shawn D. Burnham

发明人： Tahir Hussain ,  Miroslav Micovic ,  Wah S. Wong ,  Shawn D. Burnham

IPC分类号： H01L21/338

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462

摘要： A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.

摘要翻译： 一种制造具有源极和漏极的正常“关闭”GaN异质结构场效应晶体管的方法，包括沉积图案化以覆盖源极和漏极之间的沟道区域的钝化层，在钝化层中形成第一开口，第一开口 用于在所述沟道区域中限定栅极区域，并且所述第一开口沿着所述源极和漏极之间的电流流动的方向具有第一长度尺寸，以及将离子注入所述栅极区域内的注入区域中，其中所述植入区域具有第二 沿着电流流动方向的长度尺寸短于第一长度尺寸。

公开(公告)号：US08368119B1

公开(公告)日：2013-02-05

申请号：US13111771

申请日：2011-05-19

申请人： Louis Luh ,  Keh-Chung Wang ,  Wah S. Wong ,  Miroslav Micovic ,  David Chow ,  Don Hitko

发明人： Louis Luh ,  Keh-Chung Wang ,  Wah S. Wong ,  Miroslav Micovic ,  David Chow ,  Don Hitko

IPC分类号： H01L29/66

CPC分类号： H01L29/7787 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/08 ,  H01L29/872

摘要： A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.

摘要翻译： 公开了一种用于制造包括高电子迁移率晶体管（HEMT）和肖特基二极管的集成III族氮化物结构的方法及其结果。 使得垂直结肖特基二极管的集成成为可能，并且寄生电容和电阻以及二极管的物理尺寸最小化。 还公开了一种制造包括双异质结构场效应晶体管（DHFET）和肖特基二极管的集成III族氮化物结构的方法及其结果。

公开(公告)号：US07989277B1

公开(公告)日：2011-08-02

申请号：US11853694

申请日：2007-09-11

申请人： Louis Luh ,  Keh-Chung Wang ,  Wah S. Wong ,  Miroslav Micovic ,  David Chow ,  Don Hitko

发明人： Louis Luh ,  Keh-Chung Wang ,  Wah S. Wong ,  Miroslav Micovic ,  David Chow ,  Don Hitko

IPC分类号： H01L21/338

CPC分类号： H01L29/7787 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/08 ,  H01L29/872

摘要： A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.

摘要翻译： 公开了一种用于制造包括高电子迁移率晶体管（HEMT）和肖特基二极管的集成III族氮化物结构的方法及其结果。 使得垂直结肖特基二极管的集成成为可能，并且寄生电容和电阻以及二极管的物理尺寸最小化。 还公开了一种制造包括双异质结构场效应晶体管（DHFET）和肖特基二极管的集成III族氮化物结构的方法及其结果。

公开(公告)号：US5998817A

公开(公告)日：1999-12-07

申请号：US963529

申请日：1997-11-03

申请人： Cheng P. Wen ,  Peter Chu ,  Michael R. Cole ,  Wah S. Wong ,  Robert F. Wang ,  Liping D. Hou

发明人： Cheng P. Wen ,  Peter Chu ,  Michael R. Cole ,  Wah S. Wong ,  Robert F. Wang ,  Liping D. Hou

IPC分类号： H01L25/18 ,  H01L23/482 ,  H01L23/66 ,  H01L25/04 ,  H01L29/80

CPC分类号： H01L23/4824 ,  H01L23/66 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A multicell transistor for use in a circuit has an input ground plane for an input waveguide and an output ground plane for an output waveguide. The multicell transistor includes a gate electrode coupled to the input waveguide, a drain electrode coupled to the output waveguide, and a source electrode coupled to the input ground plane. An output ground strap spaced from the drain electrode couples the output ground plane to the source electrode. A pair of transmission lines are orthogonally connected to and extend from the gate electrode to form a pair of inductors for matching the impedances of the gate electrode and the input waveguide.

摘要翻译： 用于电路的多晶体管晶体管具有用于输入波导的输入接地平面和用于输出波导的输出接地平面。 多晶体管晶体管包括耦合到输入波导的栅电极，耦合到输出波导的漏电极和耦合到输入接地层的源电极。 与漏极间隔开的输出接地带将输出接地平面耦合到源电极。 一对传输线与栅电极正交连接并从栅电极延伸，形成一对用于匹配栅电极和输入波导的阻抗的电感器。

公开(公告)号：US4855796A

公开(公告)日：1989-08-08

申请号：US871236

申请日：1986-06-06

申请人： Wah S. Wong ,  Cheng P. Wen ,  Jen K. Kung

发明人： Wah S. Wong ,  Cheng P. Wen ,  Jen K. Kung

IPC分类号： H01L21/329 ,  H01L23/482 ,  H01L29/41 ,  H01L29/872

CPC分类号： H01L21/263 ,  H01L23/4822 ,  H01L24/01 ,  H01L29/41 ,  H01L29/66212 ,  H01L29/872 ,  H01L2924/12032 ,  H01L2924/3011

摘要： A beam lead diode configuration is described, employing a planar proton bombarded conversion region and a low-permittivity dielectric separator. The diode enjoys the mechanical ruggedness of the conventional planar diodes and the electrical performance of conventional mesa-type diodes. The diode structure results in the absence of N-type mesa structures on the substrate, allowing fabrication by relatively low-cost, high-yield photolithographic processes.

摘要翻译： 使用平面质子轰击转换区和低介电常数介质分离器来描述束引线二极管配置。 二极管具有常规平面二极管的机械坚固性和常规台面型二极管的电性能。 二极管结构导致在衬底上不存在N型台面结构，允许通过相对低成本的高产量光刻工艺制造。

公开(公告)号：US07514759B1

公开(公告)日：2009-04-07

申请号：US11104395

申请日：2005-04-11

申请人： Sarabjit Mehta ,  David E. Grider ,  Wah S. Wong

发明人： Sarabjit Mehta ,  David E. Grider ,  Wah S. Wong

IPC分类号： H01L29/84 ,  H01L21/00

CPC分类号： H01L29/2003 ,  B81B2201/0271 ,  B81C1/00246 ,  B81C2203/0735 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/778 ,  H01L29/812

摘要： A process for fabricating a combined micro electromechanical/gallium nitride structure. The micro electromechanical structure comprises a piezoelectric device, such as a piezoelectric switch or a bulk acoustic wave device. According to the process, high Q compact bulk acoustic wave resonators can be built. The process is applicable to technologies such as tunable planar filter technology, amplifier technology and high speed analog-to-digital converters.

摘要翻译： 一种用于制造组合的微机电/氮化镓结构的方法。 微机电结构包括压电器件，例如压电开关或体声波器件。 根据该过程，可以构建高Q小体积声波谐振器。 该过程适用于可调谐平面滤波技术，放大器技术和高速模数转换器等技术。

公开(公告)号：US5861341A

公开(公告)日：1999-01-19

申请号：US680453

申请日：1996-07-15

申请人： Cheng P. Wen ,  Wah S. Wong ,  Arlene E. Arthur

发明人： Cheng P. Wen ,  Wah S. Wong ,  Arlene E. Arthur

IPC分类号： H01L23/66 ,  H01L21/441

CPC分类号： H01L23/66 ,  H01L2924/0002

摘要： A thin film (at least one atomic layer to about 400 .ANG.) of nickel is electrolytically plated on top of electrolytically-plated gold electrodes in GaAs monolithic microwave integrated circuits (MMICs) without any additional photoresist masking step. The thin electrolytically-plated nickel film improves adhesion of a passivating dielectric layer (e.g., silicon dioxide, silicon nitride, and silicon oxynitride) formed on the electrolytically-plated gold electrodes. The electrolytically-plated nickel film can be removed locally to facilitate the fabrication of plated silver bumps (for off-chip electrical connections and thermal paths) on passivated flip chip MMICs.

摘要翻译： 在GaAs单片微波集成电路（MMIC）中的电解电镀金电极的顶部上电解电镀镍（至少一个原子层至约400）的镍膜，而无需任何额外的光刻胶掩模步骤。 薄的电解镍膜改善了在电解镀金的金电极上形成的钝化介质层（例如，二氧化硅，氮化硅和氮氧化硅）的粘附性。 可以局部去除电解镍膜，以便于在钝化倒装芯片MMIC上制造电镀银凸块（片外电连接和热路径）。

公开(公告)号：US06830945B2

公开(公告)日：2004-12-14

申请号：US10386960

申请日：2003-03-12

申请人： Jeong Sun Moon ,  Paul Hashimoto ,  Wah S. Wong ,  David E. Grider

发明人： Jeong Sun Moon ,  Paul Hashimoto ,  Wah S. Wong ,  David E. Grider

IPC分类号： H01L2100

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L21/30612 ,  H01L29/2003 ,  H01L29/7787

摘要： A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.

摘要翻译： 公开了使用具有一致的可重复结果的III族氮化物材料制造非平面异质结构场效应晶体管的方法。 该方法提供其上沉积至少一层半导体材料的衬底。 AlN层沉积在至少一层半导体材料上。 使用溶剂去除一部分AlN层以产生具有一致和可重复结果的非平面区域。 AlN层下面的至少一层不溶于溶剂，因此用作蚀刻停止层，防止对AlN层下面的至少一层的任何损坏。 此外，如果AlN层由于反应离子蚀刻而导致任何表面损伤，则当暴露于溶剂以形成非平面区域时，损伤将被去除。

公开(公告)号：US5773897A

公开(公告)日：1998-06-30

申请号：US803656

申请日：1997-02-21

申请人： Cheng P. Wen ,  Wah S. Wong

发明人： Cheng P. Wen ,  Wah S. Wong

IPC分类号： H01L23/485 ,  H01L23/66 ,  H05K1/09 ,  H01L29/46

CPC分类号： H01L23/66 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15787

摘要： Mushroom-shaped, solder-capped, small-diameter (approximately 50 to 75 microns or less), metal bumps are used in the flip chip monolithic microwave integrated circuits (MMICs) attachment process to provide devices having improved solder volume uniformity. The operation of the MMIC device is extended to millimeter-wave frequencies. The self-alignment property of the solder reflow flip chip attachment process is retained, and enhanced by the solder cap that extends beyond the periphery of the metal bump. Solder flux instead of solder paste patterns are printed on the assembly substrate to facilitate flip chip attachment. The metal bumps comprise electroplated silver pillars having a first diameter capped with electroplated solder having a second diameter, where the second diameter is larger than the first diameter, and are formed using a multi-layer negative photoresist, multiple exposure processing sequence.

摘要翻译： 在倒装芯片单片微波集成电路（MMIC）连接工艺中使用蘑菇形，焊锡封口，小直径（约50至75微米或更小）的金属凸块，以提供具有改善的焊料体积均匀性的器件。 MMIC器件的工作扩展到毫米波频率。 保留焊料回流倒装芯片附着工序的自对准性，并且通过延伸超出金属凸块周边的焊锡帽来增强。 将焊剂代替焊膏图案印刷在组件基板上以便于倒装芯片附接。 金属凸块包括具有第一直径的电镀银柱，其具有第二直径的电镀焊料，其中第二直径大于第一直径，并且使用多层负性光致抗蚀剂形成多次曝光处理顺序。

公开(公告)号：US07247893B2

公开(公告)日：2007-07-24

申请号：US10932811

申请日：2004-09-01

申请人： Jeong Sun Moon ,  Paul Hashimoto ,  Wah S. Wong ,  David E. Grider

发明人： Jeong Sun Moon ,  Paul Hashimoto ,  Wah S. Wong ,  David E. Grider

IPC分类号： H01L29/20

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L21/30612 ,  H01L29/2003 ,  H01L29/7787

摘要： A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.

摘要翻译： 公开了使用具有一致的可重复结果的III族氮化物材料制造非平面异质结构场效应晶体管的方法。 该方法提供其上沉积至少一层半导体材料的衬底。 AlN层沉积在至少一层半导体材料上。 使用溶剂去除一部分AlN层以产生具有一致和可重复结果的非平面区域。 AlN层下面的至少一层不溶于溶剂，因此用作蚀刻停止层，防止对AlN层下面的至少一层的任何损坏。 此外，如果AlN层由于反应离子蚀刻而导致任何表面损伤，则当暴露于溶剂以形成非平面区域时，损伤将被去除。