公开(公告)号：US09728511B2

公开(公告)日：2017-08-08

申请号：US14109162

申请日：2013-12-17

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Hsi-Jung Wu ,  Volume Chien ,  Ying-Lang Wang ,  Hsin-Chi Chen ,  Ying-Hao Chen ,  Hung-Ta Huang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/58 ,  H01L21/784

CPC classification number: H01L23/562 ,  H01L21/784 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.

公开(公告)号：US20150170985A1

公开(公告)日：2015-06-18

申请号：US14109162

申请日：2013-12-17

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Hsi-Jung Wu ,  Volume Chien ,  Ying-Lang Wang ,  Hsin-Chi Chen ,  Ying-Hao Chen ,  Hung-Ta Huang

IPC: H01L23/10 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/784 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.

Abstract translation: 半导体晶片包括基板，集成电路和模具密封环结构。 基板具有模具区域，围绕模具区域的模具密封环区域和围绕模具密封环区域的划线区域。 基板包括与第一表面相对的第一表面和第二表面，以及在模具密封环区域的第一表面，划线区域或模具密封环区域和划线区域内的周期性凹槽。 集成电路位于模具区域的第一表面和第二表面上。 模具密封环结构位于模具密封环区域的第二表面上。 还提供半导体管芯。

公开(公告)号：US09082617B2

公开(公告)日：2015-07-14

申请号：US14109314

申请日：2013-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Yuan Su ,  Hung-Ta Huang ,  Ping-Hao Lin ,  Hung-Che Liao ,  Hung-Yu Chiu ,  Chao-Hsuan Pan ,  Wen-Tsung Chen ,  Chih-Ming Huang

IPC: H01L23/60 ,  H01L27/02 ,  H01L27/06 ,  H01L21/8238

CPC classification number: H01L27/0255 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0262

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a semiconductor substrate, at least one deep n-well in the semiconductor substrate, at least one p-channel metal-oxide-semiconductor transistor in the deep n-well, at least one n-channel metal-oxide-semiconductor transistor outside of the deep n-well, an first interconnect structure, and a protection component. Both of the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor are disposed in the semiconductor substrate, and are electrically coupled by the first interconnect structure. The protection component is disposed in the semiconductor substrate, wherein the protection component is electrically coupled to the deep n-well.

Abstract translation: 提供集成电路和制造集成电路的方法。 在各种实施例中，集成电路包括半导体衬底，半导体衬底中的至少一个深n阱，深n阱中的至少一个p沟道金属氧化物半导体晶体管，至少一个n沟道金属 氧化物半导体晶体管，深n阱外，第一互连结构和保护部件。 p沟道金属氧化物半导体晶体管和n沟道金属氧化物半导体晶体管都设置在半导体衬底中，并通过第一互连结构电耦合。 保护元件设置在半导体衬底中，其中保护元件电耦合到深n阱。