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公开(公告)号：US09728597B2
公开(公告)日：2017-08-08
申请号：US14800144
申请日：2015-07-15
发明人： Hsing-Lien Lin , Chia-Shiung Tsai , Cheng-Yuan Tsai , Huey-Chi Chu , Hai-Dang Trinh , Wen-Chuan Chiang , Wei-Min Tseng
IPC分类号： H01L49/02 , H01L21/02 , H01L23/522
CPC分类号： H01L28/60 , H01L21/0226 , H01L21/0228 , H01L23/5223
摘要： A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.
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公开(公告)号：US09219110B2
公开(公告)日：2015-12-22
申请号：US14249482
申请日：2014-04-10
IPC分类号： H01L27/108 , H01L29/94 , H01L49/02 , H01L21/768 , H01L23/58 , H01L21/02 , H01L21/28
CPC分类号： H01L28/75 , H01L21/76805 , H01L23/5223 , H01L23/5226 , H01L23/585 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.
摘要翻译： 本发明涉及一种MIM电容器及其相关联的形成方法。 在一些实施例中，MIM电容器具有设置在半导体衬底之上的具有底部电容器金属层的第一电极。 具有中间电容器金属层的第二电极覆盖在底部电容器金属层上。 具有顶部电容器金属层的第三电极具有阶梯状结构，通过从底部电容器金属层和中间电容器金属层之间的第一位置连续延伸的电容器电介质层与中间电容器金属层横向和垂直地分离，形成为 中间电容器金属层和顶部电容器金属层之间的第二位置。 电容器介质层允许MIM电容器具有改善电容器制造的结构。
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公开(公告)号：US09391016B2
公开(公告)日：2016-07-12
申请号：US14249513
申请日：2014-04-10
IPC分类号： H01L23/522 , H01L49/02 , H01L21/3105 , H01L21/768 , H01L23/64
CPC分类号： H01L23/5223 , H01L21/31053 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L23/5226 , H01L23/64 , H01L23/642 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.
摘要翻译： 本公开涉及具有MIM（金属 - 绝缘体 - 金属）电容器和相关联的形成方法的集成芯片。 在一些实施例中，集成芯片具有设置在电容器级间电介质（ILD）层内的MIM电容器。 下部金属层设置在电容器ILD层的下方，并且包括位于MIM电容器下方的一个或多个金属结构。 多个通孔垂直延伸穿过电容器ILD层和MIM电容器。 多个通孔提供与MIM电容器和下金属层的电连接。 通过使用多个通孔来提供与MIM电容器和下金属层的垂直连接，集成芯片不使用专门为MIM电容器指定的通孔，从而降低了集成芯片制造的复杂性。
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公开(公告)号：US09368392B2
公开(公告)日：2016-06-14
申请号：US14249498
申请日：2014-04-10
IPC分类号： H01L21/02 , H01L21/768 , H01L23/48 , H01L27/08 , H01L49/02
CPC分类号： H01L21/76802 , H01L21/76805 , H01L23/481 , H01L23/5223 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.
摘要翻译： 金属 - 绝缘体 - 金属电容器技术领域本公开涉及一种MIM（金属 - 绝缘体 - 金属）电容器及其相关联的形成方法。 在一些实施例中，MIM电容器包括具有电容器底部金属层的第一电极，该电容器底部金属层设置在位于金属下层以下的介电缓冲层上。 电容器电介质层设置在电容器底部金属层上并直接接触电容器底部金属层。 具有顶部电容器金属层的第二电极设置在电容器介电层上并与其直接接触。 在顶部电容器金属层上设置电容器级间电介质层（ILD）层，以及设置在电容器ILD层上的基本上平面的蚀刻停止层。 电容器的简单堆叠提供了一个小的步长，可以防止与地形相关的问题，而介电缓冲层消除了对下层金属层的设计限制。
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公开(公告)号：US20150295020A1
公开(公告)日：2015-10-15
申请号：US14249498
申请日：2014-04-10
IPC分类号： H01L49/02 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76802 , H01L21/76805 , H01L23/481 , H01L23/5223 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.
摘要翻译： 金属 - 绝缘体 - 金属电容器技术领域本公开涉及一种MIM（金属 - 绝缘体 - 金属）电容器及其相关联的形成方法。 在一些实施例中，MIM电容器包括具有电容器底部金属层的第一电极，该电容器底部金属层设置在位于金属下层以下的介电缓冲层上。 电容器电介质层设置在电容器底部金属层上并直接接触电容器底部金属层。 具有顶部电容器金属层的第二电极设置在电容器介电层上并与其直接接触。 在顶部电容器金属层上设置电容器级间电介质层（ILD）层，以及设置在电容器ILD层上的基本平坦的蚀刻停止层。 电容器的简单堆叠提供了一个小的步长，可以防止与地形相关的问题，而介电缓冲层消除了对下层金属层的设计限制。
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公开(公告)号：US20150295019A1
公开(公告)日：2015-10-15
申请号：US14249482
申请日：2014-04-10
IPC分类号： H01L49/02 , H01L21/28 , H01L21/02 , H01L21/768 , H01L23/58
CPC分类号： H01L28/75 , H01L21/76805 , H01L23/5223 , H01L23/5226 , H01L23/585 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.
摘要翻译： 本发明涉及一种MIM电容器及其相关联的形成方法。 在一些实施例中，MIM电容器具有设置在半导体衬底之上的具有底部电容器金属层的第一电极。 具有中间电容器金属层的第二电极覆盖在底部电容器金属层上。 具有顶部电容器金属层的第三电极具有阶梯状结构，通过从底部电容器金属层和中间电容器金属层之间的第一位置连续延伸的电容器电介质层与中间电容器金属层横向和垂直地分离，形成为 中间电容器金属层和顶部电容器金属层之间的第二位置。 电容器介质层允许MIM电容器具有改善电容器制造的结构。
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公开(公告)号：US20150294936A1
公开(公告)日：2015-10-15
申请号：US14249513
申请日：2014-04-10
IPC分类号： H01L23/522 , H01L21/3105 , H01L21/768 , H01L49/02
CPC分类号： H01L23/5223 , H01L21/31053 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L23/5226 , H01L23/64 , H01L23/642 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.
摘要翻译： 本公开涉及具有MIM（金属 - 绝缘体 - 金属）电容器和相关联的形成方法的集成芯片。 在一些实施例中，集成芯片具有设置在电容器级间电介质（ILD）层内的MIM电容器。 下部金属层设置在电容器ILD层的下方，并且包括位于MIM电容器下方的一个或多个金属结构。 多个通孔垂直延伸穿过电容器ILD层和MIM电容器。 多个通孔提供与MIM电容器和下金属层的电连接。 通过使用多个通孔来提供与MIM电容器和下金属层的垂直连接，集成芯片不使用专门为MIM电容器指定的通孔，从而降低了集成芯片制造的复杂性。
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