公开(公告)号：US11527717B2

公开(公告)日：2022-12-13

申请号：US16807564

申请日：2020-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Hsing-Lien Lin ,  Tzu-Chung Tsai ,  Fa-Shen Jiang ,  Bi-Shen Lee

IPC: H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant.

公开(公告)号：US11322464B2

公开(公告)日：2022-05-03

申请号：US16589497

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Julie Yang ,  Chii-Ming Wu ,  Tzu-Chung Tsai ,  Yao-Wen Chang

IPC: H01L23/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.

公开(公告)号：US20200274058A1

公开(公告)日：2020-08-27

申请号：US15931896

申请日：2020-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hai-Dang Trinh ,  Hsing-Lien Lin ,  Chii-Ming Wu ,  Cheng-Yuan Tsai

IPC: H01L45/00 ,  G11C13/00 ,  G11C11/56

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer over the lower electrode, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. Oxygen ions are bonded more tightly in the second dielectric layer than those in the first dielectric layer, and oxygen ions are bonded more tightly in the second dielectric layer than those in the third dielectric layer.

公开(公告)号：US09929268B2

公开(公告)日：2018-03-27

申请号：US15099607

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chii-Ming Wu ,  Ru-Shang Hsiao ,  Hung Pin Chen ,  Sen-Hong Syue ,  Chi-Cherng Jeng

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method of fabricating a FinFET includes at last the following steps. A direction is determined by tilting 8.05±2 degrees from a normal vector of a (110) lattice plane of a semiconductor substrate. The semiconductor substrate is patterned along a lattice plane perpendicular to the direction, so as to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin having sidewalls disposed on a (551) lattice plane. Insulators are in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. Strained material portions are formed over the semiconductor fins revealed by the gate stack.

公开(公告)号：US20170301793A1

公开(公告)日：2017-10-19

申请号：US15099607

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chii-Ming Wu ,  Ru-Shang Hsiao ,  Hung Pin Chen ,  Sen-Hong Syue ,  Chi-Cherng Jeng

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method of fabricating a FinFET includes at last the following steps. A direction is determined by tilting 8.05±2 degrees from a normal vector of a (110) lattice plane of a semiconductor substrate. The semiconductor substrate is patterned along a lattice plane perpendicular to the direction, so as to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin having sidewalls disposed on a (551) lattice plane. Insulators are in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. Strained material portions are formed over the semiconductor fins revealed by the gate stack.

公开(公告)号：US11430729B2

公开(公告)日：2022-08-30

申请号：US17022320

申请日：2020-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Lien Lin ,  Cheng-Te Lee ,  Rei-Lin Chu ,  Chii-Ming Wu ,  Yeur-Luen Tu ,  Chung-Yi Yu

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01L21/02

Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

公开(公告)号：US11152455B2

公开(公告)日：2021-10-19

申请号：US16579738

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Lien Lin ,  Chii-Ming Wu ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Rei-Lin Chu

IPC: H01L21/00 ,  H01L23/52 ,  H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L23/64 ,  H01L27/22

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

公开(公告)号：US20210066591A1

公开(公告)日：2021-03-04

申请号：US16807564

申请日：2020-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Hsing-Lien Lin ,  Tzu-Chung Tsai ,  Fa-Shen Jiang ,  Bi-Shen Lee

IPC: H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant.

公开(公告)号：US10157770B2

公开(公告)日：2018-12-18

申请号：US15660107

申请日：2017-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/70 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure STI, and semiconductor fins. The first isolation structure is on the substrate and has a first thickness. The second isolation structure abuts the first isolation structure and has a second thickness. The first thickness is different from the second thickness. The semiconductor fins respectively abut the first isolation structure and the second isolation structure.

公开(公告)号：US09997633B2

公开(公告)日：2018-06-12

申请号：US15071206

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chii-Ming Wu

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7856 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate over the substrate. Besides, the gate include a first portion, a second portion overlying the first portion and a third portion overlying the second portion, and the critical dimension of the second portion is smaller than each of the critical dimension of the first portion and the critical dimension of the third portion.