公开(公告)号：US20250105138A1

公开(公告)日：2025-03-27

申请号：US18977704

申请日：2024-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

IPC: H01L23/522 ,  G11C11/22 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L23/532 ,  H01L27/12 ,  H01L27/146

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

公开(公告)号：US20220367637A1

公开(公告)日：2022-11-17

申请号：US17523033

申请日：2021-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chung Chen ,  Tsung-Hsin Yu ,  Chung-Hui Chen ,  Hui-Zhong Zhuang ,  Ya Yun Liu

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L21/8234

Abstract: The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 μm.

公开(公告)号：US12159904B2

公开(公告)日：2024-12-03

申请号：US17523033

申请日：2021-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chung Chen ,  Tsung-Hsin Yu ,  Chung-Hui Chen ,  Hui-Zhong Zhuang ,  Ya Yun Liu

IPC: H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 μm.

公开(公告)号：US10978449B2

公开(公告)日：2021-04-13

申请号：US16723938

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan ,  Wei-Chih Chen

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

公开(公告)号：US09748226B1

公开(公告)日：2017-08-29

申请号：US15055562

申请日：2016-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan ,  Wei-Chih Chen

IPC: H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0629 ,  H01L23/528 ,  H01L27/0207 ,  H01L28/40

Abstract: A device is disclosed that includes active areas, gates, and conductors. The active areas are disposed apart from each other. The gates are crossing over the active areas. The conductors are disposed over the active areas and disposed between the active areas. Each one of the conductors disposed between the active areas is arranged between adjacent two of the gates, and has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

公开(公告)号：US09502400B2

公开(公告)日：2016-11-22

申请号：US14808040

申请日：2015-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hui Chen

IPC: H01L27/06 ,  H01L29/06 ,  H01L49/02 ,  H01L23/522 ,  H01L29/73 ,  H01L27/02 ,  H01L23/528 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L27/067 ,  H01L21/76224 ,  H01L23/5223 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0635 ,  H01L28/40 ,  H01L28/88 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/73 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.

公开(公告)号：US09305864B2

公开(公告)日：2016-04-05

申请号：US14024925

申请日：2013-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jaw-Juinn Horng ,  Chia-Lin Yu ,  Chung-Hui Chen ,  Der-Chyang Yeh ,  Yung-Chow Peng

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

公开(公告)号：US09166067B2

公开(公告)日：2015-10-20

申请号：US14089808

申请日：2013-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jaw-Juinn Horng ,  Chung-Hui Chen ,  Sun-Jay Chang ,  Chia-Hsin Hu

IPC: H01L27/02 ,  H01L29/861 ,  H01L27/08

CPC classification number: H01L29/8611 ,  H01L27/0207 ,  H01L27/0814 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.

Abstract translation: 带隙参考电路包括耦合在第一电源节点和一对中间电压节点之间的基于误差放大器的电流镜，以及用于提供比例绝对温度（PTAT）电流的匹配二极管对。 匹配二极管对包括连接在来自一对中间电压节点的第一中间电压节点和第二电源节点之间的第一二极管，以及与来自所述一对中间电压的第二中间电压节点之间的电阻器串联连接的第二二极管 节点和第二个供应节点。 每个二极管具有一个同相结合的P-N二极管结。

公开(公告)号：US12199030B2

公开(公告)日：2025-01-14

申请号：US18446648

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

IPC: H01L23/522 ,  H01L21/84 ,  H01L23/528 ,  H01L23/532 ,  H01L27/12 ,  G11C11/22 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/146

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

公开(公告)号：US20220359375A1

公开(公告)日：2022-11-10

申请号：US17812887

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

IPC: H01L23/522 ,  H01L27/12 ,  H01L21/84 ,  H01L23/532 ,  H01L23/528

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.