公开(公告)号：US12224298B2

公开(公告)日：2025-02-11

申请号：US17391302

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsien Li ,  Yen-Ting Chiang ,  Shyh-Fann Ting ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.

公开(公告)号：US12068287B2

公开(公告)日：2024-08-20

申请号：US18170790

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Meng-Hsun Wan ,  Dun-Nian Yaung

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/03019 ,  H01L2224/033 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0384 ,  H01L2224/03848 ,  H01L2224/04105 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/08058 ,  H01L2224/08145 ,  H01L2224/80357 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2224/9202 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/80986 ,  H01L2224/80895 ,  H01L2224/8083 ,  H01L2224/9202 ,  H01L2224/03 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/00014

Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

公开(公告)号：US20240266341A1

公开(公告)日：2024-08-08

申请号：US18640167

申请日：2024-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Dun-Nian Yaung

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/06515 ,  H01L2224/08052 ,  H01L2224/08146 ,  H01L2224/0913 ,  H01L2224/09515 ,  H01L2224/09517 ,  H01L2224/48463 ,  H01L2224/8122 ,  H01L2224/81359 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437

Abstract: A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

公开(公告)号：US12057446B2

公开(公告)日：2024-08-06

申请号：US18359578

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin

IPC: H01L21/00 ,  H01L21/265 ,  H01L23/00 ,  H01L23/522 ,  H01L27/06 ,  H01L29/66 ,  H01L29/861 ,  H01L49/02

CPC classification number: H01L27/0676 ,  H01L21/26513 ,  H01L23/5226 ,  H01L24/08 ,  H01L28/40 ,  H01L29/66136 ,  H01L29/861 ,  H01L2224/08145

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

公开(公告)号：US11854959B2

公开(公告)日：2023-12-26

申请号：US17352969

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin ,  Kuan-Hua Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L28/87 ,  H01L28/91

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

公开(公告)号：US20230378139A1

公开(公告)日：2023-11-23

申请号：US18359311

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Ting Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Chia-Chieh Lin ,  U-Ting Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L23/481 ,  H01L24/92 ,  H01L21/76898 ,  H01L2224/821 ,  H01L2224/82106 ,  H01L2224/24145 ,  H01L21/76831 ,  H01L2224/9212 ,  H01L23/53223 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L24/80 ,  H01L23/53238 ,  H01L2224/9202 ,  H01L24/82 ,  H01L2924/0002 ,  H01L21/76805 ,  H01L2225/06541 ,  H01L23/53266

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

公开(公告)号：US20230207530A1

公开(公告)日：2023-06-29

申请号：US18170790

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Szu-Ying Chen ,  Meng-Hsun Wan ,  Dun-Nian Yaung

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/033 ,  H01L2224/0384 ,  H01L2224/03019 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/03848 ,  H01L2224/04105 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/08058 ,  H01L2224/8083 ,  H01L2224/08145 ,  H01L2224/9202 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/01074

Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

公开(公告)号：US20220367554A1

公开(公告)日：2022-11-17

申请号：US17391302

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsien Li ,  Yen-Ting Chiang ,  Shyh-Fann Ting ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.

公开(公告)号：US20220336505A1

公开(公告)日：2022-10-20

申请号：US17372888

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Shih-Han Huang

IPC: H01L27/146

Abstract: A metal grid within a trench isolation structure on the back side of an image sensor is coupled to a contact pad so that a voltage on the metal grid is continuously variable with a voltage on the contact pad. One or more conductive structures directly couple the metal grid to a contact pad. The conductive structures may bypass a front side of the image sensor. A bias voltage on the metal grid may be varied through the contact pad whereby a trade-off between reducing cross-talk and increasing quantum efficiency may be adjusted dynamically in accordance with the application of the image sensor, its environment of use, or its mode of operation.

公开(公告)号：US20220173092A1

公开(公告)日：2022-06-02

申请号：US17651881

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Dun-Nian Yaung

IPC: H01L25/00 ,  H01L27/146 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065

Abstract: A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.