公开(公告)号：US11735624B2

公开(公告)日：2023-08-22

申请号：US17361723

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Ru-Liang Lee ,  Ming Chyi Liu ,  Sheng-Chan Li ,  Sheng-Chau Chen

IPC: H01L27/146 ,  H01L49/02 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L28/87 ,  H01L21/768 ,  H01L23/5223 ,  H01L28/90 ,  H01L27/14603

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.

公开(公告)号：US11670725B2

公开(公告)日：2023-06-06

申请号：US16996130

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu

IPC: H01L31/02 ,  H01L31/0236 ,  G01J1/42 ,  H01L27/146 ,  H01L31/0216 ,  G01J1/04

CPC classification number: H01L31/02363 ,  G01J1/0411 ,  G01J1/42 ,  H01L27/1464 ,  H01L31/02161

Abstract: The present disclosure relates to an image sensor. The image sensor includes a substrate and a photodetector in the substrate. The image sensor further includes an absorption enhancement structure. The absorption enhancement structure is defined by a substrate depression along a first side of the substrate. The substrate depression is defined by a first plurality of sidewalls that slope toward a first common point and by a second plurality of sidewalls that slope toward a second common point. The first plurality of sidewalls extend over the second plurality of sidewalls.

公开(公告)号：US11652025B2

公开(公告)日：2023-05-16

申请号：US17150048

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Ming Chyi Liu ,  Jiech-Fun Lu

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/146

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76898 ,  H01L27/14636 ,  H01L27/1464

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) including a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate, an insulating structure disposed along inner sidewalls of the semiconductor substrate, the inner sidewalls of the semiconductor substrate extending through the semiconductor substrate, a blocking layer disposed along inner sidewalls of the insulating structure, and a through-substrate via (TSV) comprising a first portion and a second portion, the first portion extending from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure, the second portion extending from the first portion to the conductive structure and has a maximum width less than that of the first portion.

公开(公告)号：US11557710B2

公开(公告)日：2023-01-17

申请号：US16250049

申请日：2019-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Jung Chen ,  Ming Chyi Liu

IPC: H01L41/047 ,  H01L41/18 ,  H01L41/083 ,  H01L41/293 ,  H01L41/332

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a piezoelectric device including a piezoelectric membrane and a plurality of conductive layers. The method includes forming the plurality of conductive layers in the piezoelectric membrane, the plurality of conductive layers are vertically offset one another. A masking layer is formed over the piezoelectric membrane. An etch process is performed according to the masking layer to concurrently expose an upper surface of each conductive layer in the plurality of conductive layers. A plurality of conductive vias are formed over the upper surface of the plurality of conductive layers.

公开(公告)号：US20220344291A1

公开(公告)日：2022-10-27

申请号：US17366556

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: In some embodiments, the present disclosure relates to a device that includes an interconnect structure arranged on a frontside of a substrate. The interconnect structure includes interconnect conductive structures embedded within interconnect dielectric layers. A trench extends completely through the substrate to expose multiples ones of the interconnect conductive structures. A bond pad structure is arranged on a backside of the substrate and extends through the trench of the substrate to contact the multiple ones of the interconnect conductive structures. A bonding structure is arranged on the backside of the substrate and electrically contacts the bond pad structure.

公开(公告)号：US20220285412A1

公开(公告)日：2022-09-08

申请号：US17328036

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Jiech-Fun Lu

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor comprises a plurality of photodetectors disposed within a substrate. A metal grid layer is disposed over the substrate. The metal grid layer comprises a metal grid structure overlying a central pixel region of the substrate. The metal grid layer continuously extends from the central pixel region to a peripheral pixel region of the substrate that laterally encloses the central pixel region. An upper metal structure is disposed over the metal grid layer. The upper metal structure overlies the peripheral pixel region. The upper metal structure is laterally offset from the metal grid structure. A lower surface of the upper metal structure is disposed vertically over an upper surface of the metal grid structure.

公开(公告)号：US20220223425A1

公开(公告)日：2022-07-14

申请号：US17144628

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Hung-Wen Hsu ,  Min-Yung Ko

IPC: H01L21/3065 ,  H01L23/522 ,  H01L21/66 ,  H01L21/67 ,  H01J37/32

Abstract: A work piece is positioned on a work piece support, which includes a plurality of temperature control zones. A pre-etch surface topography is determined by measuring a plurality of pre-etch surface heights or thicknesses at a plurality of sites on the work piece. The plurality of sites correspond to the plurality of temperature control zones on the work piece support. At least a first zone of the temperature control zones is heated or cooled based on the measured plurality of pre-etch surface heights or thicknesses, so that the first zone has a first temperature different from a second temperature of a second zone of the temperature control zones. A dry etch is carried out while the first zone has the first temperature different from the second temperature of the second zone of the temperature control zones.

公开(公告)号：US20210376282A1

公开(公告)日：2021-12-02

申请号：US16884375

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Ming Chyi Liu

IPC: H01L51/52 ,  H01L27/32

Abstract: In some embodiments, the present disclosure relates to a display device that includes a first reflector electrode and a second reflector electrode that is separated from the first reflector electrode. The display device further includes an isolation structure that overlies the first and second reflector electrodes. The isolation structure includes a first and second portion. The first portion overlies the first reflector electrode and has a first thickness. The second portion overlies the second reflector electrode, has a second thickness greater than the first thickness, and is separated from the first portion of the isolation structure. The display device also includes a first optical emitter structure and a second optical emitter structure that respectively overlie the first portion and the second portion of the isolation structure.

公开(公告)号：US11158789B2

公开(公告)日：2021-10-26

申请号：US16575725

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L49/02

Abstract: In some methods, a contact is formed over a substrate, and a bottom electrode layer is formed over the contact. A first dielectric layer is formed to cover a peripheral portion of the bottom electrode layer but not a central portion of the bottom electrode layer. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer includes a central dielectric region that contacts the central portion of the bottom electrode layer, and a peripheral dielectric region over the peripheral portion of the bottom electrode. A step dielectric region connects the central and peripheral dielectric regions. A top electrode layer is formed over the second dielectric layer. The top electrode layer includes a central top electrode region, a peripheral top electrode region, and a step top electrode region directly above the central dielectric region, the peripheral dielectric region, and the step dielectric region, respectively.

公开(公告)号：US11152384B2

公开(公告)日：2021-10-19

申请号：US16387720

申请日：2019-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L27/11548 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/423 ,  H01L21/027

Abstract: An integrated circuits device includes a semiconductor substrate having a logic region and a memory region separated by an isolation region having an isolation structure of dielectric material. A memory device is formed on the memory region and includes a gate electrode over a gate dielectric. A dummy gate structure is formed on the isolation structure. The dummy gate structure has a dummy gate electrode layer corresponding to the gate electrode and a dummy gate dielectric layer corresponding to the gate dielectric. A tapered sidewall structure is formed on a logic region-facing side of the dummy gate structure. The tapered sidewall structure is spaced above the isolation structure and either adjacent to or contiguous with the dummy gate electrode layer.