中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.019 seconds)

    LOW gds MEASUREMENT METHODOLOGY FOR MOS
    1.
    发明申请
    LOW gds MEASUREMENT METHODOLOGY FOR MOS 有权
    MOS的测量方法

    公开(公告)号：US20150168468A1

    公开(公告)日：2015-06-18

    申请号：US14107140

    申请日：2013-12-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yung-Chow Peng ,  Po-Zeng Kang

    IPC: G01R27/08

    CPC classification number: G01R27/08 ,  G01N27/025 ,  G01R31/2621

    Abstract: A dummy MOSFET is connected in series with a device under test to form cascode structure. The conductance of the low conductance MOSFET is derived from the measurements done on the cascode structure. An open loop gain stage is connected to the cascode structure in case the signal at the internal node of the cascode structure is extremely small to be measured directly and accurately. Impedance measurements can also be done on high impedance MOS devices without noise distortion with the help of the cascode arrangement.

    Abstract translation: 虚拟MOSFET与被测器件串联连接以形成共源共栅结构。 低导通MOSFET的电导来自于在共源共栅结构上进行的测量。 在共源共栅结构的内部节点处的信号非常小以直接和准确地测量的情况下，开环增益级连接到共源共栅结构。 借助于共源共栅布置，也可以在高阻抗MOS器件上实现阻抗测量，而无噪声失真。

    IC degradation management circuit, system and method
    2.
    发明授权
    IC degradation management circuit, system and method 有权

    公开(公告)号：US10514417B2

    公开(公告)日：2019-12-24

    申请号：US16291793

    申请日：2019-03-04

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Po-Zeng Kang ,  Chih-Hsien Chang ,  Wen-Shen Chou ,  Yung-Chow Peng

    IPC: G06F17/50 ,  G01R31/28 ,  H03K3/03 ,  H03K19/20

    Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.

    NEARLY BUFFER ZONE FREE LAYOUT METHODOLOGY
    4.
    发明申请
    NEARLY BUFFER ZONE FREE LAYOUT METHODOLOGY 有权
    最近缓冲区自由布局方法

    公开(公告)号：US20150108610A1

    公开(公告)日：2015-04-23

    申请号：US14578690

    申请日：2014-12-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yung-Chow Peng ,  Jaw-Juinn Horng ,  Szu-Lin Liu ,  Po-Zeng Kang

    IPC: H01L27/02

    CPC classification number: H01L27/0207 ,  G06F17/5063 ,  G06F17/5068 ,  G06F17/5081 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In some embodiments, an integrated circuit includes a central array region having a first layout feature density. A background region surrounds the central array region and has a second layout feature density, which is different from the first density. A peripheral array region surrounds the central array region and separates the central array region from the background region. The peripheral array region has a third layout feature density between the first and second layout feature densities.

    Abstract translation: 在一些实施例中，集成电路包括具有第一布局特征密度的中心阵列区域。 背景区域围绕中心阵列区域并且具有与第一密度不同的第二布局特征密度。 外围阵列区域围绕中心阵列区域并将中心阵列区域与背景区域分离。 外围阵列区域具有第一和第二布局特征密度之间的第三布局特征密度。

    Semiconductor device feature density gradient verification
    6.
    发明授权
    Semiconductor device feature density gradient verification 有权
    半导体器件特征密度梯度校验

    公开(公告)号：US08856707B2

    公开(公告)日：2014-10-07

    申请号：US14012142

    申请日：2013-08-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Young-Chow Peng ,  Chung-Hui Chen ,  Chien-Hung Chen ,  Po-Zeng Kang

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70

    Abstract: A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.

    Abstract translation: 提供了一种用于验证半导体器件布局中存在可接受的器件特征梯度和器件特征差异的方法。 该方法提供了将设备布局划分成多个窗口并且测量或以其他方式确定每个窗口内的设备特征密度。 设备布局包括各种设备区域，并且该方法提供了将一个区域内的平均设备特征密度与周围区域或其他区域进行比较，并且还用于确定设备特征密度的梯度。 可以从特定设备区域到周围区域监视梯度。 用于执行该方法的指令可以存储在计算机可读存储介质上并由处理器执行。

    IC degradation management circuit, system and method
    9.
    发明授权
    IC degradation management circuit, system and method 有权

    公开(公告)号：US10222412B2

    公开(公告)日：2019-03-05

    申请号：US15170707

    申请日：2016-06-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Zeng Kang ,  Chih-Hsien Chang ,  Wen-Shen Chou ,  Yung-Chow Peng

    IPC: G06F17/50 ,  G01R31/28 ,  H03K3/03 ,  H03K19/20

    Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.

Patent Agency Ranking