公开(公告)号：US12245528B2

公开(公告)日：2025-03-04

申请号：US18362781

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H10N70/20 ,  H10N50/01 ,  H10N70/00

Abstract: A memory device includes a first metal structure, a magnetic tunnel junction (MTJ) structure, a second metal structure, a first spacer, and a second spacer. The MTJ structure is over the first metal structure. The second metal structure is over the MTJ structure. The first spacer is over a first sidewall of the second metal structure. The second spacer is over a second sidewall of the second metal structure. The second spacer has a top surface higher than a top surface of the first spacer.

公开(公告)号：US11495743B2

公开(公告)日：2022-11-08

申请号：US16866704

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chern-Yow Hsu ,  Chung-Chiang Min ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12

Abstract: A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.

公开(公告)号：US11258007B2

公开(公告)日：2022-02-22

申请号：US17065606

申请日：2020-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

公开(公告)号：US11158797B2

公开(公告)日：2021-10-26

申请号：US16009327

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L27/24

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

公开(公告)号：US11005037B2

公开(公告)日：2021-05-11

申请号：US15647579

申请日：2017-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L49/02

Abstract: A method of manufacturing an integrated circuit device. In the method, a plurality of contacts are formed over a substrate, and one or more bottom electrode layers are formed over the plurality of contacts. A first dielectric layer is formed such that a first base region of the first dielectric layer is in contact with the one or more bottom electrode layers and a second base region of the first dielectric layer is not in contact with the one or more bottom electrode layers. One or more top electrode layers are formed over the first dielectric layer. Patterning is then performed by etching through the one or more top electrode layers and by etching through the first dielectric layer to form a metal-insulator-metal structure. The patterning removes a portion of the second base region, but does not remove the first base region.

公开(公告)号：US20200227426A1

公开(公告)日：2020-07-16

申请号：US16387720

申请日：2019-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L27/11548 ,  H01L21/762 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11526 ,  H01L21/311

Abstract: An integrated circuits device includes a semiconductor substrate having a logic region and a memory region separated by an isolation region having an isolation structure of dielectric material. A memory device is formed on the memory region and includes a gate electrode over a gate dielectric. A dummy gate structure is formed on the isolation structure. The dummy gate structure has a dummy gate electrode layer corresponding to the gate electrode and a dummy gate dielectric layer corresponding to the gate dielectric. A tapered sidewall structure is formed on a logic region-facing side of the dummy gate structure. The tapered sidewall structure is spaced above the isolation structure and either adjacent to or contiguous with the dummy gate electrode layer.

公开(公告)号：US20200075855A1

公开(公告)日：2020-03-05

申请号：US16674445

申请日：2019-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

公开(公告)号：US10535671B2

公开(公告)日：2020-01-14

申请号：US16506207

申请日：2019-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L21/762 ,  H01L27/11521 ,  H01L21/28 ,  H01L27/11534 ,  H01L27/11548 ,  H01L27/11526 ,  H01L29/423 ,  H01L23/528

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US10522532B2

公开(公告)日：2019-12-31

申请号：US15216830

申请日：2016-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yen Chou ,  Chia-Shiung Tsai ,  Shih-Chang Liu ,  Yung-Chang Chang

IPC: H01L27/02 ,  H01L29/205 ,  H01L29/778 ,  H01L23/48 ,  H01L27/06 ,  H01L21/768 ,  H01L21/822 ,  H01L29/20

Abstract: A process for manufacturing an integrated circuit (IC) with a through via extending through a group III-V layer to a diode is provided. An etch is performed through the group III-V layer, into a semiconductor substrate underlying the group III-V layer, to form a via opening. A doped region is formed in the semiconductor substrate, through the via opening. Further, the doped region is formed with an opposite doping type as a surrounding region of the semiconductor substrate. The through via is formed in the via opening and in electrical communication with the doped region.

公开(公告)号：US10510952B2

公开(公告)日：2019-12-17

申请号：US15783030

申请日：2017-10-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L43/12 ,  H01L21/311

Abstract: A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch.