公开(公告)号：US11769693B2

公开(公告)日：2023-09-26

申请号：US17316063

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Yu-Kai Lin ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/76832 ,  H01L21/31116 ,  H01L21/7684 ,  H01L23/5329 ,  H01L23/53223 ,  H01L23/53266

Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.

公开(公告)号：US11676852B2

公开(公告)日：2023-06-13

申请号：US17119692

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Shing-Chyang Pan ,  Ching-Yu Chang ,  Wan-Lin Tsai ,  Jung-Hau Shiu ,  Tze-Liang Lee

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L21/76802 ,  H01L21/0228 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76879

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

公开(公告)号：US11594678B2

公开(公告)日：2023-02-28

申请号：US16807600

申请日：2020-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Zhong ,  Cheng-Yuan Tsai ,  Hai-Dang Trinh ,  Shing-Chyang Pan

IPC: H01L45/00 ,  H01L27/24

Abstract: Some embodiments relate to a memory device. The memory device includes a bottom electrode overlying a substrate. A data storage layer overlies the bottom electrode. A top electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode. A diffusion barrier layer is disposed between the data storage layer and the top electrode.

公开(公告)号：US10468297B1

公开(公告)日：2019-11-05

申请号：US15964306

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Yu-Kai Lin ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311

Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.

公开(公告)号：US20150162282A1

公开(公告)日：2015-06-11

申请号：US14102090

申请日：2013-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Hong-Hui Hsu

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A robust metallization profile is formed by forming two or more layers of hard mask with different density. Multi-layer metal hard mask is helpful especially in small feature size process, for example, 50 nm and below. Lower layers have higher density. In such ways, enough process window is offered by lower layers and at the same time, round hard mask profile is offered by upper layers.

Abstract translation: 通过形成具有不同密度的两层或更多层硬掩模形成坚固的金属化轮廓。 多层金属硬掩模有助于特别是在小特征尺寸过程中，例如50nm及以下。 较低的层具有较高的密度。 以这种方式，较低层提供了足够的工艺窗口，同时由上层提供圆形硬掩模。

公开(公告)号：US20150162280A1

公开(公告)日：2015-06-11

申请号：US14102072

申请日：2013-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Hong-Hui Hsu ,  Yao-Jen Chang

IPC: H01L23/522 ,  H01L21/033 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A robust metallization profile is formed by pre-treat an anti-reflective coating layer by plasma before forming a hard mask layer. Pre-treatment is helpful especially in small feature size process, for example, 50 nm and below. By changing constitution of a surface layer of the anti-reflective coating, interface of the anti-reflective coating layer and the hard mask layer is smoothed which results in less overhang and better gap-filling performance.

Abstract translation: 通过在形成硬掩模层之前通过等离子体预处理抗反射涂层来形成坚固的金属化轮廓。 预处理有助于特别是在小特征尺寸过程中，例如50nm及以下。 通过改变抗反射涂层的表面层的结构，抗反射涂层和硬掩模层的界面被平滑化，这导致较少的悬垂和更好的间隙填充性能。

公开(公告)号：US20240282571A1

公开(公告)日：2024-08-22

申请号：US18639575

申请日：2024-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Lin Tsai ,  Jung-Hau Shiu ,  Ching-Yu Chang ,  Jen Hung Wang ,  Shing-Chyang Pan ,  Tze-Liang Lee

IPC: H01L21/02 ,  C23C14/06 ,  C23C14/08 ,  C23C14/22 ,  C23C16/02 ,  C23C16/04 ,  C23C16/30 ,  C23C16/40 ,  C23C16/455 ,  H01J37/32 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/66

CPC classification number: H01L21/02126 ,  C23C14/0676 ,  C23C14/08 ,  C23C16/0245 ,  C23C16/042 ,  C23C16/045 ,  C23C16/308 ,  C23C16/401 ,  C23C16/45529 ,  C23C16/45536 ,  C23C16/45553 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/823821 ,  H01L29/66795 ,  C23C14/228 ,  H01J37/32082 ,  H01J37/32174 ,  H01L21/76808 ,  H01L23/528

Abstract: A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

公开(公告)号：US11515474B2

公开(公告)日：2022-11-29

申请号：US17112861

申请日：2020-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.

公开(公告)号：US20220254680A1

公开(公告)日：2022-08-11

申请号：US17732695

申请日：2022-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Jen-Hung Wang ,  Shing-Chyang Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

公开(公告)号：US11198606B2

公开(公告)日：2021-12-14

申请号：US16579713

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ren Wang ,  Shing-Chyang Pan ,  Yuan-Chih Hsieh

IPC: B81B7/00 ,  B81B7/02 ,  B81C1/00

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capping structure over a device substrate. The device substrate includes a first microelectromechanical systems (MEMS) device and a second MEMS device laterally offset from the first MEMS device. The capping structure includes a first cavity overlying the first MEMS device and a second cavity overlying the second MEMS device. The first cavity has a first gas pressure and the second cavity has a second gas pressure different from the first cavity. An outgas layer abutting the first cavity. The outgas layer includes an outgas material having an outgas species. The outgas material is amorphous.