公开(公告)号：US12278162B2

公开(公告)日：2025-04-15

申请号：US18366481

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsun Wang ,  Ping-Yin Hsieh ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L25/18

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.

公开(公告)号：US12255079B2

公开(公告)日：2025-03-18

申请号：US17884037

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chuan Chang ,  Szu-Wei Lu ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages. Corresponding structures result from these methods.

公开(公告)号：US20240395727A1

公开(公告)日：2024-11-28

申请号：US18790119

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.

公开(公告)号：US20240272352A1

公开(公告)日：2024-08-15

申请号：US18324576

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tsung-Fu Tsai ,  Chih-Hao Yu ,  Jui Lin Chao ,  Szu-Wei Lu

IPC: G02B6/12 ,  G02B6/136

CPC classification number: G02B6/12004 ,  G02B6/136 ,  G02B2006/12121

Abstract: A method includes connecting a first photonic package to a substrate, wherein the first photonic package includes a first waveguide and a first support over the first waveguide; connecting a second photonic package to the substrate adjacent the first photonic package, wherein the second photonic package includes a second waveguide, wherein the first photonic package and the second photonic package are laterally separated by a gap that has a width in the range of 15 μm to 190 μm; depositing a first quantity of an optical adhesive into the gap; and curing the first quantity of the optical adhesive, wherein after curing the first quantity of the optical adhesive, the first waveguide is optically coupled to the second waveguide through the first quantity of the optical adhesive.

公开(公告)号：US11990429B2

公开(公告)日：2024-05-21

申请号：US17994548

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Kung-Chen Yeh ,  Li-Chung Kuo ,  Pu Wang ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L21/31053 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/18 ,  H01L25/50

Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

公开(公告)号：US11929261B2

公开(公告)日：2024-03-12

申请号：US17097857

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chuan Chang ,  Szu-Wei Lu ,  Chen-Hua Yu

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0655 ,  H01L2224/0233 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.

公开(公告)号：US20240071982A1

公开(公告)日：2024-02-29

申请号：US17895321

申请日：2022-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jung Chen ,  Tsung-Fu Tsai ,  Szu-Wei Lu

IPC: H01L23/00

CPC classification number: H01L24/74 ,  H01L24/80 ,  H01L21/56 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/80203 ,  H01L2224/808

Abstract: In an embodiment, a device bonding apparatus is provided. The device bonding apparatus includes a first process station configured to receive a wafer; a first bond head configured to carry a die to the wafer, wherein the first bonding head includes a first rigid body and a vacuum channel in the first rigid body for providing an attaching force for carrying the die to the wafer; and a second bond head configured to press the die against the wafer, the second bond head including a second rigid body and an elastic head disposed over the second rigid body for pressing the die, the elastic head having a center portion and an edge portion surrounding the center portion, the center portion of the elastic head having a first thickness, the edge portion of the elastic head having a second thickness, the second thickness being greater than the second thickness.

公开(公告)号：US11901255B2

公开(公告)日：2024-02-13

申请号：US17869003

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Pan ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/3157 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657

Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.

公开(公告)号：US20230402345A1

公开(公告)日：2023-12-14

申请号：US17806532

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen Chiang Yu ,  Tsung-Fu Tsai ,  Szu-Wei Lu

IPC: H01L23/367 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L21/4882

Abstract: A semiconductor package including a cooling system and a method of forming are provided. The semiconductor package may include an interposer, one or more package components bonded to the interposer, an encapsulant on the interposer, and a cooling system over the one or more package components. The cooling system may include one or more metal layers on top surfaces of the one or more package components, first metal pins on the one or more metal layers, second metal pins, wherein each of the second metal pins may be bonded to a corresponding one of the first metal pins by solder, and a first lid over the second metal pins, wherein the first lid may include openings.

公开(公告)号：US20230387057A1

公开(公告)日：2023-11-30

申请号：US18365362

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chih Chiou ,  Chen-Hua Yu ,  Shih Ting Lin ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L24/08 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/80 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/486 ,  H01L2924/35121 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.