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公开(公告)号：US20180349545A1
公开(公告)日：2018-12-06
申请号：US16059367
申请日：2018-08-09
发明人： Hung-Chun Wang , Ming-Hui Chih , Ping-Chieh Wu , Chun-Hung Wu , Wen-Hao Liu , Cheng-Hsuan Huang , Cheng-Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
CPC分类号： G06F17/5081 , G03F1/36
摘要： The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.
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公开(公告)号：US20160275232A1
公开(公告)日：2016-09-22
申请号：US15170026
申请日：2016-06-01
发明人： Hung-Chun Wang , Ming-Hui Chih , Ping-Chieh Wu , Chun-Hung Wu , Wen-Hao Liu , Cheng-Hsuan Huang , Cheng-Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
CPC分类号： G06F17/5081 , G03F1/36
摘要： The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.
摘要翻译： 本公开涉及一种利用低OPC（光学邻近校正）周期时间改进图案密度的方法，以及相关联的装置。 在一些实施例中，通过对包括用于制造集成芯片的布局的图形表示的IC设计执行初始数据准备处理来执行该方法。 通过使用数据准备元件来进行初始数据准备处理，以生成具有改进形状的修改的IC设计，其是IC设计中的形状的修改形式。 使用局部密度检查元件来识别修改的IC设计的一个或多个低图案密度区域。 使用虚拟形状插入元件在一个或多个低图案密度区域内添加一个或多个虚拟形状。 一个或多个虚拟形状通过非零空间与修改后的形状分离。
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公开(公告)号：US10049178B2
公开(公告)日：2018-08-14
申请号：US15170026
申请日：2016-06-01
发明人： Hung-Chun Wang , Ming-Hui Chih , Ping-Chieh Wu , Chun-Hung Wu , Wen-Hao Liu , Cheng-Hsuan Huang , Cheng-Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
摘要： The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.
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公开(公告)号：US10860774B2
公开(公告)日：2020-12-08
申请号：US16059367
申请日：2018-08-09
发明人： Hung-Chun Wang , Ming-Hui Chih , Ping-Chieh Wu , Chun-Hung Wu , Wen-Hao Liu , Cheng-Hsuan Huang , Cheng-Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G06F30/398 , G03F1/36
摘要： The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.
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公开(公告)号：US20150106779A1
公开(公告)日：2015-04-16
申请号：US14051549
申请日：2013-10-11
发明人： Hung-Chun Wang , Ming-Hui Chih , Ping-Chieh Wu , Chun-Hung Wu , Wen-Hao Liu , Cheng-Hsuan Huang , Cheng-Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.
摘要翻译： 本公开涉及一种利用低OPC（光学邻近校正）周期时间改进图案密度的方法，以及相关联的装置。 在一些实施例中，该方法通过形成作为集成芯片的图形表示的集成芯片（IC）设计来执行。 识别IC设计中的一个或多个低图案密度区域具有导致处理失败的图案密度。 低图案密度区域是IC设计的一个子集。 通过在低图案密度区域内添加一个或多个虚拟形状，在低图案密度区域内调整图案密度。 然后对IC设计执行数据准备处理，以修改低图案密度区域内的一个或多个虚拟形状的形状。 通过将虚拟形状引入局部区域而不是整个集成芯片设计中，随后的数据准备过程的需求减少。
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公开(公告)号：US09411924B2
公开(公告)日：2016-08-09
申请号：US14051549
申请日：2013-10-11
发明人： Hung-Chun Wang , Ming-Hui Chih , Ping-Chieh Wu , Chun-Hung Wu , Wen-Hao Liu , Cheng-Hsuan Huang , Cheng-Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
CPC分类号： G06F17/5081 , G03F1/36
摘要： The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.
摘要翻译： 本公开涉及一种利用低OPC（光学邻近校正）周期时间改进图案密度的方法，以及相关联的装置。 在一些实施例中，该方法通过形成作为集成芯片的图形表示的集成芯片（IC）设计来执行。 识别IC设计中的一个或多个低图案密度区域具有导致处理失败的图案密度。 低图案密度区域是IC设计的一个子集。 通过在低图案密度区域内添加一个或多个虚拟形状，在低图案密度区域内调整图案密度。 然后对IC设计执行数据准备处理，以修改低图案密度区域内的一个或多个虚拟形状的形状。 通过将虚拟形状引入局部区域而不是整个集成芯片设计中，随后的数据准备过程的需求减少。
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