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公开(公告)号：US11791299B2
公开(公告)日：2023-10-17
申请号：US15965116
申请日：2018-04-27
发明人： Cheng-Yuan Li , Kuo-Cheng Lee , Yun-Wei Cheng , Yen-Liang Lin
IPC分类号： H01L23/00
CPC分类号： H01L24/20 , H01L24/24 , H01L24/82 , H01L2224/2105 , H01L2224/24145 , H01L2224/8212 , H01L2224/82896
摘要： Exemplary embodiments for redistribution layers of integrated circuits are disclosed. The redistribution layers of integrated circuits of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.
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公开(公告)号：US11626339B2
公开(公告)日：2023-04-11
申请号：US17201856
申请日：2021-03-15
发明人： Tzu-Sung Huang , Ming Hung Tseng , Yen-Liang Lin , Hao-Yi Tsai , Chi-Ming Tsai , Chung-Shi Liu , Chih-Wei Lin , Ming-Che Ho
IPC分类号： H01L23/31 , H01L23/16 , H01L23/522 , H01L21/768 , H01L21/56 , H01L23/528
摘要： In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
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公开(公告)号：US20200058689A1
公开(公告)日：2020-02-20
申请号：US16662453
申请日：2019-10-24
发明人： Chia-Yu Wei , Hsin-Chi Chen , Kuo-Cheng Lee , Ping-Hao Lin , Hsun-Ying Huang , Yen-Liang Lin , Yu Ting Kao
IPC分类号： H01L27/146
摘要： The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
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公开(公告)号：US20190326240A1
公开(公告)日：2019-10-24
申请号：US16458324
申请日：2019-07-01
发明人： Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen , Yen-Liang Lin
摘要： The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.
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公开(公告)号：US09893107B2
公开(公告)日：2018-02-13
申请号：US14857657
申请日：2015-09-17
发明人： Chia-Yu Wei , Hsin-Chi Chen , Ssu-Chiang Weng , Yung-Lung Hsu , Yen-Liang Lin , Chin-Hsun Hsiao
IPC分类号： H01L27/146
CPC分类号： H01L27/14643 , H01L27/14609 , H01L27/1463 , H01L27/14689
摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a light sensing feature, a negative oxide layer, a gate dielectric layer and a transfer gate. The light sensing feature is configured in the substrate to detect an incoming radiation. The negative oxide layer is over the light sensing feature. The gate dielectric layer is over the negative oxide layer. The transfer gate is over the gate dielectric layer.
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公开(公告)号：US09379151B1
公开(公告)日：2016-06-28
申请号：US14600949
申请日：2015-01-20
发明人： Chia-Yu Wei , Yin-Chen Chen , Yen-Liang Lin , Yung-Lung Hsu , Hsin-Chi Chen
IPC分类号： H01L27/148 , H01L27/146
CPC分类号： H01L27/14614 , H01L27/14638 , H01L27/14643 , H01L27/14689 , H01L27/148
摘要： An image sensor device is provided, and includes pixel units. Each of the pixel units includes a light sensing element, a first transistor and a second transistor. The first transistor is coupled to the light sensing element. The second transistor is coupled to the light sensing element and the first transistor. The first transistor includes a first gate structure having a first width, and the second transistor includes a second gate structure having a second width, in which a distance between the first gate structure and the second gate structure is substantially greater than the first width and the second width.
摘要翻译： 提供了图像传感器装置，并且包括像素单元。 每个像素单元包括光感测元件，第一晶体管和第二晶体管。 第一晶体管耦合到感光元件。 第二晶体管耦合到光感测元件和第一晶体管。 第一晶体管包括具有第一宽度的第一栅极结构，并且第二晶体管包括具有第二宽度的第二栅极结构，其中第一栅极结构和第二栅极结构之间的距离基本上大于第一宽度， 第二宽度。
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公开(公告)号：US11973050B2
公开(公告)日：2024-04-30
申请号：US17336888
申请日：2021-06-02
发明人： Tzu-Yu Lin , Yao-Wen Chang , Chia-Wen Zhong , Yen-Liang Lin
IPC分类号： H01L23/522 , H01L21/3213 , H01L23/00 , H01L27/15
CPC分类号： H01L24/20 , H01L21/32139 , H01L23/5226 , H01L24/13 , H01L24/19 , H01L27/15 , H01L2224/13019 , H01L2224/2101
摘要： Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.
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公开(公告)号：US20230245939A1
公开(公告)日：2023-08-03
申请号：US18297927
申请日：2023-04-10
发明人： Tzu-Sung Huang , Ming Hung Tseng , Yen-Liang Lin , Hao-Yi Tsai , Chi-Ming Tsai , Chung-Shi Liu , Chih-Wei Lin , Ming-Che Ho
IPC分类号： H01L23/31 , H01L23/16 , H01L23/522 , H01L21/768 , H01L21/56 , H01L23/528
CPC分类号： H01L23/3157 , H01L23/16 , H01L23/5226 , H01L21/76843 , H01L21/56 , H01L21/76802 , H01L23/528
摘要： In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
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公开(公告)号：US11456263B2
公开(公告)日：2022-09-27
申请号：US16907838
申请日：2020-06-22
发明人： Chia-Yu Wei , Cheng-Yuan Li , Yen-Liang Lin , Kuo-Cheng Lee , Hsun-Ying Huang , Hsin-Chi Chen
IPC分类号： H01L23/00 , H01L27/146
摘要： A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first bonding layer formed below a first substrate, a first bonding via formed through the first oxide layer and the first bonding layer, a first dummy pad formed in the first bonding layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over a second substrate, a second bonding via formed through the second bonding layer, and a second dummy pad formed in the second bonding layer. The semiconductor structure includes a bonding structure between the first substrate and the second substrate, wherein the bonding structure includes the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.
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公开(公告)号：US11183523B2
公开(公告)日：2021-11-23
申请号：US16662453
申请日：2019-10-24
发明人： Chia-Yu Wei , Hsin-Chi Chen , Kuo-Cheng Lee , Ping-Hao Lin , Hsun-Ying Huang , Yen-Liang Lin , Yu Ting Kao
IPC分类号： H01L27/146
摘要： The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
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