公开(公告)号：US08949749B2

公开(公告)日：2015-02-03

申请号：US13657992

申请日：2012-10-23

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Hung-Chun Wang ,  Shao-Yun Fang ,  Tzu-Chin Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines.

Abstract translation: 本公开涉及一种用于创建用于电子束光刻的物理布局的方法和装置，包括定义用于物理设计的布局网格，所述布局网格还包括垂直网格线，其与由物理设计分割所产生的缝合线重合 多个子场。 物理设计根据设计形状和布局网格之间相互作用的设计限制进行组装。 在一些实施例中，通过布局限制来实现设计限制。 在一些实施例中，通过移动标准单元以在后布局步骤中最小化与布局格栅的设计形状交互来实现设计限制。 在一些实施例中，通过交换多个标准单元之间的位置来实现设计限制，用于交换置换，其最小化后布局步骤中的交互次数。 在一些实施例中，路由网格被改进以排除设计构造的子集与布局网格之间的交互。 然后沿着布线网格相对于缝合线优化剩余的设计形状布局。

公开(公告)号：US20150149969A1

公开(公告)日：2015-05-28

申请号：US14611331

申请日：2015-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Shao-Yun Fang ,  Tzu-Chin Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines.

Abstract translation: 本公开涉及一种用于创建用于电子束光刻的物理布局的方法和装置，包括定义用于物理设计的布局网格，所述布局网格还包括垂直网格线，其与由物理设计分割所产生的缝合线重合 多个子场。 物理设计根据设计形状和布局网格之间相互作用的设计限制进行组装。 在一些实施例中，通过布局限制来实现设计限制。 在一些实施例中，通过移动标准单元以在后布局步骤中最小化与布局格栅的设计形状交互来实现设计限制。 在一些实施例中，通过交换多个标准单元之间的位置来实现设计限制，用于交换置换，其最小化后布局步骤中的交互次数。 在一些实施例中，路由网格被改进以排除设计构造的子集与布局网格之间的交互。 然后沿着布线网格相对于缝合线优化剩余的设计形状布局。

公开(公告)号：US09165106B2

公开(公告)日：2015-10-20

申请号：US14611331

申请日：2015-02-02

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Hung-Chun Wang ,  Shao-Yun Fang ,  Tzu-Chin Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines.

公开(公告)号：US20140115546A1

公开(公告)日：2014-04-24

申请号：US13657992

申请日：2012-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Hung-Chun Wang ,  Shao-Yun Fang ,  Tzu-Chin Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines.

Abstract translation: 本公开涉及一种用于创建用于电子束光刻的物理布局的方法和装置，包括定义用于物理设计的布局网格，所述布局网格还包括垂直网格线，其与由物理设计分割所产生的缝合线重合 多个子场。 物理设计根据设计形状和布局网格之间相互作用的设计限制进行组装。 在一些实施例中，通过布局限制来实现设计限制。 在一些实施例中，通过移动标准单元以在后布局步骤中最小化与布局格栅的设计形状交互来实现设计限制。 在一些实施例中，通过交换多个标准单元之间的位置来实现设计限制，用于交换置换，其最小化后布局步骤中的交互次数。 在一些实施例中，路由网格被改进以排除设计构造的子集与布局网格之间的交互。 然后沿着布线网格相对于缝合线优化剩余的设计形状布局。