公开(公告)号：US20240096781A1

公开(公告)日：2024-03-21

申请号：US18186209

申请日：2023-03-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Ti Lu ,  Hao-Yi Tsai ,  Chia-Hung Liu ,  Yu-Hsiang Hu ,  Hsiu-Jen Lin ,  Tzuan-Horng Liu ,  Chih-Hao Chang ,  Bo-Jiun Lin ,  Shih-Wei Chen ,  Hung-Chun Cho ,  Pei-Rong Ni ,  Hsin-Wei Huang ,  Zheng-Gang Tsai ,  Tai-You Liu ,  Po-Chang Shih ,  Yu-Ting Huang

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H10B80/00

CPC分类号： H01L23/49894 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

公开(公告)号：US11637010B2

公开(公告)日：2023-04-25

申请号：US16895800

申请日：2020-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L21/764 ,  H01L23/528

摘要： The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

公开(公告)号：US09905457B2

公开(公告)日：2018-02-27

申请号：US14583514

申请日：2014-12-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bo-Jiun Lin ,  Ching-Yu Chang ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01B3/20 ,  H01L23/532

CPC分类号： H01L21/76837 ,  H01B3/20 ,  H01L21/02118 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02282 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/53233 ,  H01L23/5329

摘要： A method for forming an interconnect structure includes forming a patterned layer over a substrate, the patterned layer having an opening therein. A dielectric material is filled in the opening. The dielectric material has a precursor and a solvent, the solvent having a boiling point temperature greater than a precursor cross-linking temperature. A thermal treatment is performed on the dielectric material to form a dielectric layer.

公开(公告)号：US09709905B2

公开(公告)日：2017-07-18

申请号：US14850532

申请日：2015-09-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bo-Jiun Lin ,  Hai-Ching Chen ,  Hsin-Chieh Yao ,  Tien-I Bao

IPC分类号： G03F7/20 ,  G03F9/00 ,  G01N21/88 ,  G01N21/956 ,  H01L21/027 ,  H01L21/66

CPC分类号： G03F9/7069 ,  G01N21/8806 ,  G01N21/956 ,  G01N2021/8822 ,  G01N2021/8825 ,  G01N2021/95676 ,  G01N2201/061 ,  G01N2201/06113 ,  G03F7/70633 ,  H01L21/027 ,  H01L22/12 ,  H01L22/20

摘要： A method for fabricating a semiconductor structure includes providing a substrate and a first layer over the substrate, wherein the first layer includes one or more overlay marks. The method further includes forming one or more layers on the first layer and performing a dark field (DF) inspection on the one or more overlay marks underlying the one or more layers to receive a post-film-formation data.

公开(公告)号：US09134633B2

公开(公告)日：2015-09-15

申请号：US14138743

申请日：2013-12-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bo-Jiun Lin ,  Hsin-Chieh Yao ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： G03F9/00 ,  H01L21/66 ,  G01N21/88 ,  H01L21/027 ,  G01N21/956

CPC分类号： G03F9/7069 ,  G01N21/8806 ,  G01N21/956 ,  G01N2021/8822 ,  G01N2021/8825 ,  G01N2021/95676 ,  G01N2201/061 ,  G01N2201/06113 ,  G03F7/70633 ,  H01L21/027 ,  H01L22/12 ,  H01L22/20

摘要： The present disclosure provides a method for fabricating a semiconductor structure. The method comprises providing a substrate and a patterned layer formed on the substrate, one or more overlay marks being formed on the patterned layer; performing a pre-film-formation overlay inspection using a bright field (BF) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer; forming one or more layers on the patterned layer; performing a post-film-formation overlay inspection using a dark field (DF) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; and determining whether the pre-film-formation data matches the post-film-formation data.

摘要翻译： 本公开提供了一种用于制造半导体结构的方法。 该方法包括提供衬底和形成在衬底上的图案层，在图案化层上形成一个或多个覆盖标记; 使用亮场（BF）检查工具进行预膜形成覆盖检查，以在图案化层上的一个或多个覆盖标记上接收预成膜数据; 在所述图案化层上形成一层或多层; 使用暗场（DF）检查工具进行后期成膜覆盖检查，以接收关于所述一个或多个层下面的一个或多个覆盖标记的后期成膜数据; 以及确定成膜前数据是否与成膜后数据相匹配。

公开(公告)号：US11957070B2

公开(公告)日：2024-04-09

申请号：US17395471

申请日：2021-08-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung-Ying Lee ,  Bo-Jiun Lin ,  Shao-Ming Yu ,  Yu-Chao Lin

IPC分类号： H10N70/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/826 ,  H01L23/5283 ,  H10B63/80 ,  H10N70/061 ,  H10N70/231 ,  H10N70/841

摘要： A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

公开(公告)号：US20230299003A1

公开(公告)日：2023-09-21

申请号：US18321077

申请日：2023-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bo-Jiun Lin ,  Ching-Yu Chang ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L29/06 ,  H01L23/522 ,  H01L23/485 ,  H01L23/528 ,  H01L23/58 ,  H01L23/31

CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/02282 ,  H01L21/02216 ,  H01L21/02203 ,  H01L21/02126 ,  H01L21/7682 ,  H01L23/53295 ,  H01L29/0649 ,  H01L23/522 ,  H01L23/485 ,  H01L23/528 ,  H01L23/585 ,  H01L23/3178 ,  H01L29/0642 ,  H01L23/3185 ,  H01L2221/1047

摘要： A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

公开(公告)号：US20230045290A1

公开(公告)日：2023-02-09

申请号：US17395471

申请日：2021-08-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung-Ying Lee ,  Bo-Jiun Lin ,  Shao-Ming Yu ,  Yu-Chao Lin

IPC分类号： H01L45/00 ,  H01L27/24 ,  H01L23/528

摘要： A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

公开(公告)号：US20180254212A1

公开(公告)日：2018-09-06

申请号：US15970596

申请日：2018-05-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/02

CPC分类号： H01L21/7685 ,  C23C18/1216 ,  C23C18/1254 ,  C23C18/1295 ,  C23C18/14 ,  C23C30/00 ,  C25D3/38 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1015 ,  H01L2221/1021 ,  H01L2221/1073 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer.

公开(公告)号：US20240196764A1

公开(公告)日：2024-06-13

申请号：US18583864

申请日：2024-02-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung-Ying Lee ,  Bo-Jiun Lin ,  Shao-Ming Yu ,  Yu-Chao Lin

IPC分类号： H10N70/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/826 ,  H01L23/5283 ,  H10B63/80 ,  H10N70/061 ,  H10N70/231 ,  H10N70/841

摘要： A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.