公开(公告)号：US11957070B2

公开(公告)日：2024-04-09

申请号：US17395471

申请日：2021-08-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Ying Lee ,  Bo-Jiun Lin ,  Shao-Ming Yu ,  Yu-Chao Lin

IPC: H10N70/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H01L23/5283 ,  H10B63/80 ,  H10N70/061 ,  H10N70/231 ,  H10N70/841

Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

公开(公告)号：US20230299003A1

公开(公告)日：2023-09-21

申请号：US18321077

申请日：2023-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Ching-Yu Chang ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L29/06 ,  H01L23/522 ,  H01L23/485 ,  H01L23/528 ,  H01L23/58 ,  H01L23/31

CPC classification number: H01L23/5329 ,  H01L21/76837 ,  H01L21/02282 ,  H01L21/02216 ,  H01L21/02203 ,  H01L21/02126 ,  H01L21/7682 ,  H01L23/53295 ,  H01L29/0649 ,  H01L23/522 ,  H01L23/485 ,  H01L23/528 ,  H01L23/585 ,  H01L23/3178 ,  H01L29/0642 ,  H01L23/3185 ,  H01L2221/1047

Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

公开(公告)号：US20230045290A1

公开(公告)日：2023-02-09

申请号：US17395471

申请日：2021-08-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Ying Lee ,  Bo-Jiun Lin ,  Shao-Ming Yu ,  Yu-Chao Lin

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

公开(公告)号：US20180254212A1

公开(公告)日：2018-09-06

申请号：US15970596

申请日：2018-05-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/7685 ,  C23C18/1216 ,  C23C18/1254 ,  C23C18/1295 ,  C23C18/14 ,  C23C30/00 ,  C25D3/38 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1015 ,  H01L2221/1021 ,  H01L2221/1073 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer.

公开(公告)号：US20250063770A1

公开(公告)日：2025-02-20

申请号：US18451096

申请日：2023-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Tung-Ying Lee ,  Yu-Chao Lin

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor device including a substrate, a semiconductor layer, a gate, a dielectric structure, and a source/drain structure is provided. The semiconductor layer is disposed on the substrate, and is made of a first low dimensional material. The gate is disposed on the substrate and overlaps the semiconductor layer. The dielectric structure is disposed on the semiconductor layer and includes a trench structure reaching a portion of the semiconductor layer. The source/drain structure includes a barrier layer made of a second low dimensional material continuously extending along the trench structure and a metal fill filling a volume surrounded by the barrier layer.

公开(公告)号：US20240413222A1

公开(公告)日：2024-12-12

申请号：US18333508

申请日：2023-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Tsung-En Lee ,  Tung-Ying Lee ,  Chao-Ching Cheng

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a channel layer, an adhesion layer disposed over the channel layer, a first hafnium-containing dielectric layer disposed over the adhesion layer, a second hafnium-containing dielectric layer disposed over the first hafnium-containing dielectric layer, a gate structure, and source and drain terminals. The second hafnium-containing dielectric layer has a hafnium content lower than a hafnium content of the first hafnium-containing dielectric layer. A dielectric constant of the second hafnium-containing dielectric layer is larger than a dielectric constant of the first hafnium-containing dielectric layer.

公开(公告)号：US20240379417A1

公开(公告)日：2024-11-14

申请号：US18779106

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Tung-Ying Lee ,  Yu-Chao Lin

IPC: H01L21/768

Abstract: Provided is an interconnect structure including: a first conductive feature, disposed in a first dielectric layer; a second conductive feature, disposed over the first conductive feature and the first dielectric layer; a via, disposed between the first and second conductive features and being in direct contact with the first and second conductive features; and a barrier structure, lining a sidewall and a portion of a bottom surface of the second conductive feature, a sidewall of the via, a portion of a top surface of the first conductive feature, and a top surface of the first dielectric layer.

公开(公告)号：US20240096781A1

公开(公告)日：2024-03-21

申请号：US18186209

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Ti Lu ,  Hao-Yi Tsai ,  Chia-Hung Liu ,  Yu-Hsiang Hu ,  Hsiu-Jen Lin ,  Tzuan-Horng Liu ,  Chih-Hao Chang ,  Bo-Jiun Lin ,  Shih-Wei Chen ,  Hung-Chun Cho ,  Pei-Rong Ni ,  Hsin-Wei Huang ,  Zheng-Gang Tsai ,  Tai-You Liu ,  Po-Chang Shih ,  Yu-Ting Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L23/49894 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

公开(公告)号：US11637010B2

公开(公告)日：2023-04-25

申请号：US16895800

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L21/764 ,  H01L23/528

Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

公开(公告)号：US09905457B2

公开(公告)日：2018-02-27

申请号：US14583514

申请日：2014-12-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Ching-Yu Chang ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/768 ,  H01L21/02 ,  H01B3/20 ,  H01L23/532

CPC classification number: H01L21/76837 ,  H01B3/20 ,  H01L21/02118 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02282 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/53233 ,  H01L23/5329

Abstract: A method for forming an interconnect structure includes forming a patterned layer over a substrate, the patterned layer having an opening therein. A dielectric material is filled in the opening. The dielectric material has a precursor and a solvent, the solvent having a boiling point temperature greater than a precursor cross-linking temperature. A thermal treatment is performed on the dielectric material to form a dielectric layer.