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公开(公告)号：US12057390B2
公开(公告)日：2024-08-06
申请号：US17752704
申请日：2022-05-24
Inventor： Chi-Yu Lu , Yi-Hsun Chiu , Chih-Liang Chen , Chih-Yu Lai , Shang-Hsuan Chiu
IPC: H01L23/522 , H01L23/498 , H01L23/528 , H01L29/06
CPC classification number: H01L23/5226 , H01L23/49827 , H01L23/5286 , H01L29/0649
Abstract: An integrated circuit (IC) structure includes first and second active areas extending in a first direction in a semiconductor substrate, first and second gate structures extending in a second direction perpendicular to the first direction, wherein each of the first and second gate structures overlies each of the first and second active areas, a first metal-like defined (MD) segment extending in the second direction between the first and second gate structures and overlying each of the first and second active areas, and an isolation structure positioned between the first MD segment and the first active area. The first MD segment is electrically connected to the second active area and electrically isolated from a portion of the first active area between the first and second gate structures.
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公开(公告)号：US12019969B2
公开(公告)日：2024-06-25
申请号：US17383153
申请日：2021-07-22
Inventor： Jung-Chan Yang , Hui-Zhong Zhuang , Ting-Wei Chiang , Chi-Yu Lu
IPC: G06F30/398 , G03F1/36 , G03F1/70 , G06F30/30 , G06F30/392 , G06F30/394 , G06F30/3953 , G06F119/18
CPC classification number: G06F30/398 , G03F1/36 , G03F1/70 , G06F30/30 , G06F30/392 , G06F30/394 , G06F30/3953 , G06F2119/18
Abstract: An integrated circuit includes at least one source/drain (S/D) line extending in second direction in a cell of the integrated circuit. The integrated circuit further includes a conductive element extending in a first direction in the cell of the integrated circuit, the first direction being perpendicular to the second direction. The integrated circuit further includes a power rail extending over the conductive element, wherein the power rail includes a first power rail portion and a second power rail portion, and an inner edge of the first power rail portion is offset from an inner edge of the second power rail portion, wherein the first power rail portion has a first edge and the second power rail portion has a second edge on the same side as the first edge of the first power rail portion, and the first edge and the second edge are laterally separated.
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公开(公告)号：US12009362B2
公开(公告)日：2024-06-11
申请号：US18360539
申请日：2023-07-27
Inventor： Chih-Yu Lai , Chih-Liang Chen , Chi-Yu Lu , Shang-Syuan Ciou , Hui-Zhong Zhuang , Ching-Wei Tsai , Shang-Wen Chang
IPC: H01L27/06 , G06F30/392 , G06F30/394 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8234 , H01L23/48 , H01L23/528 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/786
CPC classification number: H01L27/0694 , G06F30/392 , G06F30/394 , H01L21/0259 , H01L21/76898 , H01L21/8221 , H01L21/823412 , H01L21/823475 , H01L23/481 , H01L23/5283 , H01L29/0665 , H01L29/41733 , H01L29/42392 , H01L29/66742 , H01L29/78696
Abstract: A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.
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公开(公告)号：US11983475B2
公开(公告)日：2024-05-14
申请号：US18165411
申请日：2023-02-07
Inventor： Pin-Dai Sue , Po-Hsiang Huang , Fong-Yuan Chang , Chi-Yu Lu , Sheng-Hsiung Chen , Chin-Chou Liu , Lee-Chung Lu , Yen-Hung Lin , Li-Chun Tien , Yi-Kan Cheng
IPC: G06F30/00 , G06F30/373 , G06F30/392 , G06F30/394 , G06F111/20
CPC classification number: G06F30/392 , G06F30/373 , G06F30/394 , G06F2111/20
Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.
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公开(公告)号：US11790151B2
公开(公告)日：2023-10-17
申请号：US17885106
申请日：2022-08-10
Inventor： Fong-Yuan Chang , Chin-Chou Liu , Hui-Zhong Zhuang , Meng-Kai Hsu , Pin-Dai Sue , Po-Hsiang Huang , Yi-Kan Cheng , Chi-Yu Lu , Jung-Chou Tsai
IPC: G06F30/398 , G06F30/392 , G06F30/394 , G06F119/18
CPC classification number: G06F30/398 , G06F30/392 , G06F30/394 , G06F2119/18
Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
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公开(公告)号：US11281836B2
公开(公告)日：2022-03-22
申请号：US17222021
申请日：2021-04-05
Inventor： Fong-Yuan Chang , Jyun-Hao Chang , Sheng-Hsiung Chen , Ho Che Yu , Lee-Chung Lu , Ni-Wan Fan , Po-Hsiang Huang , Chi-Yu Lu , Jeo-Yen Lee
IPC: G06F30/392 , H01L27/118 , G06F30/398 , G06F30/39 , H01L23/538 , H01L27/02
Abstract: A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.
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公开(公告)号：US11216608B2
公开(公告)日：2022-01-04
申请号：US16664242
申请日：2019-10-25
Inventor： Chi-Yu Lu , Hui-Zhong Zhuang , Li-Chun Tien , Pin-Dai Sue , Yi-Hsin Ko
IPC: G06F30/392 , G06F30/398
Abstract: A semiconductor device comprising at least one modified cell block that includes a modified abutment region in which is provided a first continuous active region arranged along a first axis parallel to a vertical abutment edge for positioning adjacent other cell blocks to form a vertical abutment, including non-standard, standard, and modified cell blocks. The structure provided within the modified abutment region improves a structural and device density match between the modified cell block and the adjacent cell block, thereby reducing the need for white space between vertically adjacent cell blocks and reducing the total device area and increasing cell density.
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公开(公告)号：US11093684B2
公开(公告)日：2021-08-17
申请号：US16659305
申请日：2019-10-21
Inventor： Jung-Chan Yang , Ting-Wei Chiang , Hui-Zhong Zhuang , Chi-Yu Lu
IPC: G06F30/00 , G06F30/398 , G03F1/70 , G03F1/36 , G06F30/30 , G06F30/3953 , G06F119/18
Abstract: A method for designing an integrated circuit includes steps of selecting a power rail of a cell, determining that a clearance distance for an electrical connection to or around the power rail is not sufficient to fit the electrical connection, selecting a power rail portion of the power rail for modification, and modifying a shape of the power rail portion to provide a clearance distance sufficient to fit the electrical connection. As clearance distances between features in an interconnection structure of an integrated circuit become smaller, manufacturing becomes more difficult and error-prone. Increasing clearance distances improves manufacturability of an integrated circuit. Modifying the shape of an integrated circuit power rail increases clearance distance to and/or around a power rail.
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公开(公告)号：US10163883B2
公开(公告)日：2018-12-25
申请号：US15183112
申请日：2016-06-15
Inventor： Cheok-Kei Lei , Yu-Chi Li , Chia-Wei Tseng , Zhe-Wei Jiang , Chi-Lin Liu , Jerry Chang-Jui Kao , Jung-Chan Yang , Chi-Yu Lu , Hui-Zhong Zhuang
IPC: G06F17/50 , H01L23/50 , H01L27/02 , H01L23/528 , H01L23/532
Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
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公开(公告)号：US12216981B2
公开(公告)日：2025-02-04
申请号：US18448143
申请日：2023-08-10
Inventor： Fong-Yuan Chang , Chin-Chou Liu , Hui-Zhong Zhuang , Meng-Kai Hsu , Pin-Dai Sue , Po-Hsiang Huang , Yi-Kan Cheng , Chi-Yu Lu , Jung-Chou Tsai
IPC: G06F30/398 , G06F30/392 , G06F30/394 , G06F119/18
Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
