公开(公告)号：US12002813B2

公开(公告)日：2024-06-04

申请号：US17461370

申请日：2021-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yu-Hung Cheng ,  Ching I Li ,  Chia-Shiung Tsai

IPC分类号： H01L27/12 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105

CPC分类号： H01L27/1207 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31051

摘要： A method for forming an SOI substrate is provided. The method includes following operations. A recycle substrate is received. A first multilayered structure is formed on the recycle substrate. A trench is formed in the first multilayered structure. A lateral etching is performed to remove portions of sidewalls of the trench to form a recess in the first multilayered structure. The trench and the recess are sealed with an epitaxial layer, and a potential cracking interface is formed in the first multilayered structure. A second multilayered structure is formed over the first multilayered structure. The device layer of the recycle substrate is bonded to an insulator layer over an carrier substrate. The first multilayered structure is cleaved along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate. The device layer is exposed.

公开(公告)号：US20240170326A1

公开(公告)日：2024-05-23

申请号：US18423137

申请日：2024-01-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L21/762 ,  H01L21/768

CPC分类号： H01L21/76254 ,  H01L21/76256 ,  H01L21/76877

摘要： A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.

公开(公告)号：US11894408B2

公开(公告)日：2024-02-06

申请号：US17347001

申请日：2021-06-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ping-Yin Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen ,  Pin-Nan Tseng

IPC分类号： H01L27/146

CPC分类号： H01L27/1464 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.

公开(公告)号：US20230377946A1

公开(公告)日：2023-11-23

申请号：US18363725

申请日：2023-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L21/762 ,  H01L21/768

CPC分类号： H01L21/76254 ,  H01L21/76256 ,  H01L21/76877

摘要： A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

公开(公告)号：US20230187478A1

公开(公告)日：2023-06-15

申请号：US18067776

申请日：2022-12-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsing-Lien Lin ,  Chii-Ming Wu ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Rei-Lin Chu

IPC分类号： H01L23/64 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L28/60 ,  H01L21/0234 ,  H01L21/02252 ,  H01L21/02315 ,  H01L21/76825 ,  H01L21/76841 ,  H01L23/642 ,  H10B61/10

摘要： Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

公开(公告)号：US11282697B2

公开(公告)日：2022-03-22

申请号：US16569019

申请日：2019-09-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Xin-Hua Huang ,  Ping-Yin Liu ,  Hung-Hua Lin ,  Hsun-Chung Kuang ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： B23K1/00 ,  H01L21/02 ,  B23K1/20 ,  B23K20/02 ,  B23K20/233 ,  B23K20/24 ,  H01L23/00 ,  B23K101/40 ,  B23K101/42

摘要： A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

公开(公告)号：US11276587B2

公开(公告)日：2022-03-15

申请号：US16688608

申请日：2019-11-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hui Huang ,  Chun-Han Tsao ,  Sheng-Chau Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： H01L21/67 ,  H01L21/18 ,  H01L21/762 ,  H01L21/683 ,  H01L21/687 ,  H01L21/66

摘要： An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.

公开(公告)号：US20220069068A1

公开(公告)日：2022-03-03

申请号：US17501269

申请日：2021-10-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsing-Lien Lin ,  Chii-Ming Wu ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Rei-Lin Chu

IPC分类号： H01L49/02 ,  H01L23/64 ,  H01L21/768 ,  H01L27/22 ,  H01L21/02

摘要： Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

公开(公告)号：US11037978B2

公开(公告)日：2021-06-15

申请号：US16658355

申请日：2019-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ping-Yin Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen ,  Pin-Nan Tseng

IPC分类号： H01L27/146

摘要： A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.

公开(公告)号：US10937956B2

公开(公告)日：2021-03-02

申请号：US16235816

申请日：2018-12-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chern-Yow Hsu ,  Wei-Hang Huang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L27/12 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22

摘要： A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.