公开(公告)号：US20240363722A1

公开(公告)日：2024-10-31

申请号：US18769246

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Ting CHEN ,  Tsai-Jung Ho ,  Tsung-Han Ko ,  Tetsuji Ueno ,  Yahru Cheng ,  Chen-Han Wang ,  Keng-Chu Lin ,  Shuen-Shin Liang ,  Tsu-Hsiu Perng

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L29/0653 ,  H01L29/6656

Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

公开(公告)号：US20240355805A1

公开(公告)日：2024-10-24

申请号：US18304350

申请日：2023-04-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Ting Yeh ,  Zheng-Yong Liang ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L25/00 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L24/08 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/08145 ,  H01L2224/80896 ,  H01L2224/83862

Abstract: Provided is a method of forming a semiconductor structure including: bonding a device wafer onto a carrier wafer; forming a support structure between an edge of the device wafer and an edge of the carrier wafer, wherein the support structure surrounds a device layer of the device wafer along a closed path; removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.

公开(公告)号：US11817384B2

公开(公告)日：2023-11-14

申请号：US17567525

申请日：2022-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shuen-Shin Liang ,  Ken-Yu Chang ,  Hung-Yi Huang ,  Chien Chang ,  Chi-Hung Chuang ,  Kai-Yi Chu ,  Chun-I Tsai ,  Chun-Hsien Huang ,  Chih-Wei Chang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Keng-Chu Lin ,  Sung-Li Wang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5228

Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.

公开(公告)号：US11362212B2

公开(公告)日：2022-06-14

申请号：US16572812

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mrunal A Khaderbad ,  Keng-Chu Lin ,  Sung-Li Wang

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A structure includes a transistor including a first source/drain region, a source/drain contact plug over and electrically coupling to the first source/drain region, and a via over and contacting the source/drain contact plug. The via has a bottom portion having a first length, and an upper portion having a second length. The first length is greater than the second length. Both of the first length and the second length are measured in a same direction parallel to a top surface of the source/drain contact plug.

公开(公告)号：US11217524B1

公开(公告)日：2022-01-04

申请号：US16900622

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shuen-Shin Liang ,  Ken-Yu Chang ,  Hung-Yi Huang ,  Chien Chang ,  Chi-Hung Chuang ,  Kai-Yi Chu ,  Chun-I Tsai ,  Chun-Hsien Huang ,  Chih-Wei Chang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Keng-Chu Lin ,  Sung-Li Wang

IPC: H01L23/522 ,  H01L21/768

Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.

公开(公告)号：US09728402B2

公开(公告)日：2017-08-08

申请号：US14832565

申请日：2015-08-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Cheng Wang ,  Chun-Hao Hsu ,  Han-Ti Hsiaw ,  Keng-Chu Lin

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/02348 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/76224 ,  H01L29/66795

Abstract: An embodiment is a method including depositing a first flowable film over a substrate in a processing region, the first flowable film comprising silicon and nitrogen, curing the first flowable film in a first step at a first temperature with a first process gas and ultra-violet light, the first process gas including oxygen, curing the first flowable film in a second step at a second temperature with a second process gas and ultra-violet light, the second process gas being different than the first process gas, and annealing the cured first flowable film at a third temperature to convert the cured first flowable film into a silicon oxide film over the substrate.

公开(公告)号：US20160086865A1

公开(公告)日：2016-03-24

申请号：US14949206

申请日：2015-11-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L21/66 ,  H01L21/768

CPC classification number: H01L22/26 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

Abstract translation: 一种方法包括蚀刻晶片上的低k电介质层以在低k电介质层中形成开口。 测量晶片中有害物质的量以获得测量结果。 响应于测量结果确定用于烘烤晶片的工艺条件。 使用确定的工艺条件烘烤晶片。

公开(公告)号：US09177918B2

公开(公告)日：2015-11-03

申请号：US14523707

申请日：2014-10-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Yun Peng ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Hui-Chun Yang

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/02 ,  H01L21/3105 ,  C23C16/40 ,  C23C16/52 ,  C23C16/56 ,  H01L21/768

CPC classification number: H01L23/5329 ,  C23C16/401 ,  C23C16/52 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31058 ,  H01L21/7682 ,  H01L23/562 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH3 to SiOnetwork bonds of less than or equal to 0.25; and performing a cure for a cure time to remove substantially all of the porogen from the dielectric film. In one embodiment the porogen comprises a cyclic hydrocarbon. The porogen may be UV curable. In embodiments, different lowered Si—CH3 to SiOnetwork ratios for the deposition of the dielectric film are disclosed. An apparatus of a semiconductor device including the low k dielectric layers is disclosed.

Abstract translation: 多孔SiCOH的低k电介质层的方法和装置。 一种方法包括将半导体衬底放置在气相沉积室中; 将反应性气体引入气相沉积室以形成包含SiCOH和可分解致孔剂的电介质膜; 沉积介电膜以使Si-CH3与SiO网络键的比例小于或等于0.25; 并进行固化固化时间以从电介质膜基本上除去所有致孔剂。 在一个实施方案中，致孔剂包含环状烃。 造孔剂可以是UV固化的。 在实施例中，公开了用于沉积电介质膜的不同降低的Si-CH 3与SiO网络比。 公开了一种包括低k电介质层的半导体器件的装置。

公开(公告)号：US20150270189A1

公开(公告)日：2015-09-24

申请号：US14733573

申请日：2015-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Joung-Wei Liou ,  Hui-Chun Yang ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L23/31 ,  H01L23/48

CPC classification number: H01L21/76879 ,  H01L21/02123 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/31 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.

Abstract translation: 提供了一种用于低k电介质层的系统和方法。 优选的实施方案包括形成基质并在基质内形成致孔剂。 致孔剂包括具有少于15个碳原子和大量单键的有机环结构。 此外，致孔剂可能具有大于1.3的粘度和小于0.5的雷诺数。

公开(公告)号：US09004914B2

公开(公告)日：2015-04-14

申请号：US13915287

申请日：2013-06-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Chi Ko ,  Chia Cheng Chou ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Shwang-Ming Jeng ,  Mei-Ling Chen

IPC: A01H5/02 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/70 ,  H01L21/02

CPC classification number: H01L21/768 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/70 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828

Abstract: An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller.

Abstract translation: 主动能量辅助（AEA）烘烤室包括AEA光源组件和加热器底座。 AEA烘烤室还包括控制器，用于控制输入到AEA光源组件的功率和对加热器基座的功率输入。 在衬底上形成互连的方法包括蚀刻衬底并湿式清洗蚀刻的衬底。 该方法还包括在湿清洗之后对基材进行活性能量助剂（AEA）的烘烤。 AEA烘烤包括将基板放置在AEA室中的加热器基座上，将基板暴露于等于或大于400nm的波长的光，其中所述光由光源发射并控制光源和加热器基座 使用控制器。