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公开(公告)号：US10727117B2
公开(公告)日：2020-07-28
申请号：US16130690
申请日：2018-09-13
Inventor： Yu-Hsiang Liao , Ya-Huei Li , Li-Wei Chu , Chun-Wen Nieh , Hung-Yi Huang , Chih-Wei Chang , Ching-Hwanq Su
IPC: H01L21/768 , H01L21/285 , H01L29/40 , H01L29/78 , H01L29/66
Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.
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公开(公告)号：US10032764B2
公开(公告)日：2018-07-24
申请号：US15257355
申请日：2016-09-06
Inventor： Wun-Jie Lin , Yu-Ti Su , Li-Wei Chu , Bo-Ting Chen
IPC: H01L27/02 , H01L29/78 , H01L21/8238 , H01L29/66 , H01L27/092 , H01L21/762 , H01L21/8234 , H01L29/06 , H01L29/08 , H01L27/088
Abstract: In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure.
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公开(公告)号：US20250038524A1
公开(公告)日：2025-01-30
申请号：US18359052
申请日：2023-07-26
Inventor： Jam-Wem Lee , Wun-Jie Lin , Chia-Jung Chang , Li-Wei Chu
IPC: H02H9/04
Abstract: Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.
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公开(公告)号：US12100702B2
公开(公告)日：2024-09-24
申请号：US18489652
申请日：2023-10-18
Inventor： Li-Wei Chu , Wun-Jie Lin , Yu-Ti Su , Ming-Fu Tsai , Jam-Wem Lee
CPC classification number: H01L27/0248 , H01L29/0649
Abstract: A method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. The method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. The method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. The method further includes trimming the lines into line segments having ends over the isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.
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公开(公告)号：US11837598B2
公开(公告)日：2023-12-05
申请号：US17459878
申请日：2021-08-27
Inventor： Li-Wei Chu , Wun-Jie Lin , Yu-Ti Su , Ming-Fu Tsai , Jam-Wem Lee
CPC classification number: H01L27/0248 , H01L29/0649
Abstract: A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.
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公开(公告)号：US20230344221A1
公开(公告)日：2023-10-26
申请号：US17727022
申请日：2022-04-22
Inventor： Li-Wei Chu , Tao Yi Hung , Chia-Hui Chen , Wun-Jie Lin , Jam-Wem Lee
IPC: H02H9/04
CPC classification number: H02H9/046
Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
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公开(公告)号：US20240088650A1
公开(公告)日：2024-03-14
申请号：US18513889
申请日：2023-11-20
Inventor： Li-Wei Chu , Tao Yi Hung , Chia-Hui Chen , Wun-Jie Lin , Jam-Wem Lee
IPC: H02H9/04
CPC classification number: H02H9/046
Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
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公开(公告)号：US11901353B2
公开(公告)日：2024-02-13
申请号：US17200527
申请日：2021-03-12
Inventor： Wei-Min Wu , Ming-Dou Ker , Chun-Yu Lin , Li-Wei Chu
CPC classification number: H01L27/0248 , H01L29/7412 , H01L29/7436
Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.
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公开(公告)号：US11309217B2
公开(公告)日：2022-04-19
申请号：US15909682
申请日：2018-03-01
Inventor： Ya-Huei Li , Li-Wei Chu , Yu-Hsiang Liao , Hung-Yi Huang , Chih-Wei Chang , Ching-Hwanq Su
IPC: H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/66 , H01L21/027 , H01L21/311 , H01L21/321
Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.
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公开(公告)号：US20190273024A1
公开(公告)日：2019-09-05
申请号：US15909682
申请日：2018-03-01
Inventor： Ya-Huei Li , Li-Wei Chu , Yu-Hsiang Liao , Hung-Yi Huang , Chih-Wei Chang , Ching-Hwanq Su
IPC: H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.
