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公开(公告)号：US08954899B2
公开(公告)日：2015-02-10
申请号：US13645256
申请日：2012-10-04
Inventor： Ping-Chieh Wu , Tzu-Chin Lin , Hung-Ting Lu , Wen-Chun Huang , Ru-Gun Liu
Abstract: The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour.
Abstract translation: 本公开描述了校准轮廓的方法。 该方法包括设计锚定图案，在基板上印刷锚图案，在基板上收集印刷的锚图案的扫描电子显微镜（SEM）数据，其中SEM数据包括印刷的锚图案在基板上的SEM图像， 将印刷的锚定图案的SEM图像转印到印刷锚定图案的SEM轮廓上，分析印刷的锚图案的SEM轮廓，并对准锚定图案的SEM轮廓以形成校准的SEM轮廓。
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公开(公告)号：US11790145B2
公开(公告)日：2023-10-17
申请号：US17853758
申请日：2022-06-29
Inventor： Chia-Ping Chiang , Ming-Hui Chih , Chih-Wei Hsu , Ping-Chieh Wu , Ya-Ting Chang , Tsung-Yu Wang , Wen-Li Cheng , Hui En Yin , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau
CPC classification number: G06F30/39 , G03F1/70 , G03F7/70466
Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
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公开(公告)号：US10360339B2
公开(公告)日：2019-07-23
申请号：US15043961
申请日：2016-02-15
Inventor： Hung-Chun Wang , Ching-Hsu Chang , Chun-Hung Wu , Cheng Kun Tsai , Feng-Ju Chang , Feng-Lung Lin , Ming-Hsuan Wu , Ping-Chieh Wu , Ru-Gun Liu , Wen-Chun Huang , Wen-Hao Liu
Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.
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公开(公告)号：US20150143304A1
公开(公告)日：2015-05-21
申请号：US14081521
申请日：2013-11-15
Inventor： Ming-Hui Chih , Wen-Li Cheng , Yu-Po Tang , Ping-Chieh Wu , Chia-Ping Chiang , Yong-Cheng Lin , Wen-Chun Huang , Ru-Gun Liu
IPC: G06F17/50
CPC classification number: G06F17/5009 , G03F7/70441
Abstract: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour.
Abstract translation: 由计算机处理系统执行的方法包括：接收集成电路的设计模式，向设计模式应用功能以产生模型轮廓，沿着模型轮廓生成多个光学邻近校正（OPC）目标点，调整 设计图案，以创建调整图案，并对经调整的图案进行模拟以创建模拟轮廓。
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公开(公告)号：US12159092B2
公开(公告)日：2024-12-03
申请号：US18226677
申请日：2023-07-26
Inventor： Chia-Ping Chiang , Ming-Hui Chih , Chih-Wei Hsu , Ping-Chieh Wu , Ya-Ting Chang , Tsung-Yu Wang , Wen-Li Cheng , Hui En Yin , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau
Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
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公开(公告)号：US10747938B2
公开(公告)日：2020-08-18
申请号：US16516853
申请日：2019-07-19
Inventor： Hung-Chun Wang , Ching-Hsu Chang , Chun-Hung Wu , Cheng Kun Tsai , Feng-Ju Chang , Feng-Lung Lin , Ming-Hsuan Wu , Ping-Chieh Wu , Ru-Gun Liu , Wen-Chun Huang , Wen-Hao Liu
IPC: G06F17/50 , G06F30/398 , G03F7/20 , G03F1/36 , H01L27/02 , G06F30/39 , G06F119/18
Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.
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公开(公告)号：US20190340330A1
公开(公告)日：2019-11-07
申请号：US16516853
申请日：2019-07-19
Inventor： Hung-Chun Wang , Ching-Hsu Chang , Chun-Hung Wu , Cheng Kun Tsai , Feng-Ju Chang , Feng-Lung Lin , Ming-Hsuan WU , Ping-Chieh Wu , Ru-Gun Liu , Wen-Chun Huang , Wen-Hao Liu
Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.
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公开(公告)号：US09262578B2
公开(公告)日：2016-02-16
申请号：US14293050
申请日：2014-06-02
Inventor： Hung-Chun Wang , Ching-Hsu Chang , Feng-Ju Chang , Chun-Hung Wu , Ping-Chieh Wu , Wen-Hao Liu , Ming-Hsuan Wu , Feng-Lung Lin , Cheng Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
CPC classification number: G06F17/5081 , G03F1/36 , G03F7/70441
Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.
Abstract translation: 提供了一种集成电路（IC）制造方法。 该方法包括接收IC的设计布局，其中设计布局包括多个不重叠的IC区域，并且每个IC区域包括相同的初始IC图案。 该方法还包括基于位置效应分析将IC区域分成多个组，使得相应组中的所有IC区域具有基本上相同的位置效果。 该方法还包括使用包括位置效应的校正模型对每个组中的一个IC区域进行校正; 并将校正后的IC区域复制到各组的其他IC区域。 该方法还包括将经修正的IC设计布局存储在有形的计算机可读介质中以供另外的IC处理级使用。
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公开(公告)号：US09189587B2
公开(公告)日：2015-11-17
申请号：US14045242
申请日：2013-10-03
Inventor： I-Chang Shih , Jen-Chieh Lo , Tzu-Chin Lin , Ping-Chieh Wu , Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F2217/06 , G06F2217/84
Abstract: A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes assigning a critical point value to each of the critical points within each set of critical points, analyzing a path through the integrated circuit design across multiple integrated circuit design layers, and determining a sum of critical point values of each critical point along the path.
Abstract translation: 提供了一种方法和计算机程序，用于分析集成电路设计中的一组层，以确定该层集合内每层的一组临界点。 关键点至少部分基于制造商具体的工艺参数。 该方法包括将关键点值分配给每组临界点内的每个临界点，分析跨多个集成电路设计层的集成电路设计的路径，以及确定沿着每个临界点的临界点值的总和 路径。
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公开(公告)号：US20160162627A1
公开(公告)日：2016-06-09
申请号：US15043961
申请日：2016-02-15
Inventor： Hung-Chun Wang , Ching-Hsu Chang , Chun-Hung Wu , Cheng Kun Tsai , Feng-Ju Chang , Feng-Lung Lin , Ming-Hsuan WU , Ping-Chieh Wu , Ru-Gun Liu , Wen-Chun Huang , Wen-Hao Liu
CPC classification number: G06F17/5081 , G03F1/36 , G03F7/70441 , G06F17/5068 , G06F2217/12 , H01L27/0207
Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.
Abstract translation: 提供了一种集成电路（IC）制造方法。 该方法包括接收IC设计布局，其中IC设计布局包括多个IC区域，并且每个IC区域包括初始IC图案。 该方法还包括对第一IC区域执行校正处理，从而修改第一IC区域中的初始IC图案，以产生第一IC区域中的第一校正IC图案，其中校正处理包括位置效果校正。 该方法还包括用第一校正IC图案替换第二IC区域中的初始IC图案。
